DIE Delay Lines 176

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Part	Manufacturer	Logic IC Type	Temperature Grade	Terminal Form	No. of Terminals	Package Code	Package Shape	Package Body Material	Nominal Total Delay (td)	Surface Mount	No. of Functions	No. of Taps/Steps	Technology	Programmable Delay Line	Nominal Supply Voltage / Vsup (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	Terminal Pitch	Maximum Operating Temperature	Minimum Operating Temperature	Terminal Finish	Terminal Position	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Supply Voltage (Vsup)	Qualification	Output Polarity	Minimum Supply Voltage (Vsup)	Maximum Power Supply Current (ICC)	Additional Features	JESD-609 Code	Peak Reflow Temperature (C)	Family	Maximum Input Frequency (fmax)
DS1012(DIE)-D33	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	11.5 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		TWO INDEPENDENT BUFFERED DELAYS PER INPUT; OUT3 = D3 NAND D4, OUT4 = D3 XOR D4	e0		CMOS/TTL	14.4928 MHz
DS1012(DIE)-D20	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	16.5 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		TWO INDEPENDENT BUFFERED DELAYS PER INPUT; OUT3 = D3 NAND D4, OUT4 = D3 XOR D4	e0		CMOS/TTL	10.101 MHz
DS1003-40	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	14.2 ns	YES	1	4	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V	125 mA	DELAY FROM INPUT TO 4 TAPS[NS] = 6,10,10.2,14.2; MAX FAN OUT OF 4 LSTTL/CMOS LOAD PER OUTPUT	e0		CMOS/TTL	83.33 MHz
DS1010(DIE)-300	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	300 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	2.08333 MHz
DS1013(DIE)-10	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	10 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	33.3333 MHz
DS1040(DIE)-A20	Maxim Integrated	PULSE GENERATOR DELAY LINE	COMMERCIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED		YES	1	5	CMOS	YES	5		UNCASED CHIP				70 Cel	0 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	COMPLEMENTARY	4.75 V		SILICON PULSE GENERATOR; PULSE WIDTH CHANGE PER STEP = 2.5NS	e0		CMOS/TTL	14.2857 MHz
DS1007(DIE)-10	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	40 ns	YES	7	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY ARE GUARANTEED FOR OUT5 THROUGH OUT7	e0		CMOS/TTL	8.33333 MHz
DS1012(DIE)-D50	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	9 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		TWO INDEPENDENT BUFFERED DELAYS PER INPUT; OUT3 = D3 NAND D4, OUT4 = D3 XOR D4	e0		CMOS/TTL	18.5185 MHz
DS1010(DIE)-60	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	60 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	10.4167 MHz
DS1000-45	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	45 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	13.8889 MHz
DS1010(DIE)-75	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	75 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	8.33333 MHz
DS1007(DIE)-3	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	10 ns	YES	7	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		7 INDEPENDENT BUFFERED DELAYS DELAY[NS] = 3,3,3,3,10,10,10	e0		CMOS/TTL	33.3333 MHz
DS1000-175	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	175 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	3.57143 MHz
DS1013(DIE)-25	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	25 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	13.3333 MHz
DS1040(DIE)-B50	Maxim Integrated	PULSE GENERATOR DELAY LINE	COMMERCIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED		YES	1	5	CMOS	YES	5		UNCASED CHIP				70 Cel	0 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	COMPLEMENTARY	4.75 V		SILICON PULSE GENERATOR; PULSE WIDTH CHANGE PER STEP = 5NS	e0		CMOS/TTL	10 MHz
DS1000(DIE)-450	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	450 ns	YES	1	5	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	1.38889 MHz
DS1000-250	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	250 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0	245	CMOS/TTL	2.5 MHz
DS1000-100	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	100 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	Tin/Lead (Sn85Pb15)	UPPER	X-XUUC-N	1	5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	6.25 MHz
DS1013(DIE)-75	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	75 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	4.44444 MHz
DS1013(DIE)-40	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	40 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	8.33333 MHz
DS1000-35	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	35 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	17.8571 MHz
DS1000-125	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	125 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	5 MHz
DS1012(DIE)-V50	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	20 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		TWO INDEPENDENT BUFFERED DELAYS PER INPUT; OUT3 = D3 NAND D4, OUT4 = D3 XOR D4	e0		CMOS/TTL	8.33333 MHz
DS1013(DIE)-45	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	45 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	7.40741 MHz
DS1005(DIE)-125	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	125 ns	YES	1	5	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	5 MHz
DS1000-20	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	20 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	1	5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	31.25 MHz
DS1005(DIE)-250	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	250 ns	YES	1	5	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	2.5 MHz
DS1010(DIE)-250	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	250 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	2.5 MHz
DS1012(DIE)-D25	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	14 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		TWO INDEPENDENT BUFFERED DELAYS PER INPUT; OUT3 = D3 NAND D4, OUT4 = D3 XOR D4	e0		CMOS/TTL	11.9048 MHz
DS1005(DIE)-60	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	60 ns	YES	1	5	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	10.4167 MHz
DS1000-25	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	25 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	1	5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	25 MHz
DS1040(DIE)-75	Maxim Integrated	PULSE GENERATOR DELAY LINE	COMMERCIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED		YES	1	5	CMOS	YES	5		UNCASED CHIP				70 Cel	0 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	COMPLEMENTARY	4.75 V		SILICON PULSE GENERATOR; PULSE WIDTH CHANGE PER STEP = 15NS	e0		CMOS/TTL	8 MHz
DS1010(DIE)-150	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	150 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	4.16667 MHz
DS1005(DIE)-150	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	150 ns	YES	1	5	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	4.16667 MHz
DS1013(DIE)-200	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	200 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	1.66667 MHz
DS1010(DIE)-450	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	450 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	1.38889 MHz
DS1012(DIE)-7	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	15 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		DELAY TRAILING EDGE[TYP.] = +-1NS OVER LEADING EDGE DELAY	e0		CMOS/TTL	11.1111 MHz
DS1012(DIE)-2	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	10 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		TWO INDEPENDENT BUFFERED DELAYS PER INPUT; OUT2 IS INVERTED, OUT3 = D3 AND D4, OUT4 = D3 OR D4	e0		CMOS/TTL	16.6667 MHz
DS1010(DIE)-500	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	500 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	1.25 MHz
DS1013(DIE)-80	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	80 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	4.16667 MHz
DS1010(DIE)-125	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	125 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	5 MHz
DS1013(DIE)-12	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	12 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	27.7778 MHz
DS1010(DIE)-100	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	100 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	6.25 MHz
DS1013(DIE)-30	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	30 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	11.1111 MHz
DS1040(DIE)-200	Maxim Integrated	PULSE GENERATOR DELAY LINE	COMMERCIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED		YES	1	5	CMOS	YES	5		UNCASED CHIP				70 Cel	0 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	COMPLEMENTARY	4.75 V		SILICON PULSE GENERATOR; PULSE WIDTH CHANGE PER STEP = 40NS; OUTPUT PULSE WIDTH	e0		CMOS/TTL	4 MHz
DS1040(DIE)-250	Maxim Integrated	PULSE GENERATOR DELAY LINE	COMMERCIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED		YES	1	5	CMOS	YES	5		UNCASED CHIP				70 Cel	0 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	COMPLEMENTARY	4.75 V		SILICON PULSE GENERATOR; PULSE WIDTH CHANGE PER STEP = 50NS	e0		CMOS/TTL	3.33333 MHz
DS1013(DIE)-50	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	50 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	6.66667 MHz
DS1010(DIE)-350	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	350 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N		5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0		CMOS/TTL	1.78571 MHz

Delay Lines

A delay line is an electronic component used in digital systems to introduce a delay or a time lag in a signal. Delay lines are commonly used in digital systems that require precise timing, synchronization, or control of signals.

Delay lines can be passive or active, depending on the method used to introduce the delay in the signal. Passive delay lines use passive components, such as capacitors, inductors, and resistors, to introduce the delay in the signal. Active delay lines use active components, such as amplifiers, to introduce the delay in the signal.

Delay lines can also be fixed or variable, depending on whether the delay introduced in the signal is fixed or can be adjusted. Fixed delay lines introduce a fixed delay in the signal, while variable delay lines can be adjusted to introduce a variable delay in the signal.

Delay lines are often used in digital systems that require precise timing or synchronization between different components or devices. For example, in a memory system, a delay line may be used to ensure that the signals sent to and received from the memory chips are synchronized and aligned with the clock signal.

Delay lines can also be used to compensate for signal propagation delays caused by long transmission lines or cables. In this case, the delay line is used to introduce a delay in the signal to compensate for the delay caused by the transmission line or cable.