UNSPECIFIED Delay Lines 158

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Part	Manufacturer	Logic IC Type	Temperature Grade	Terminal Form	No. of Terminals	Package Code	Package Shape	Package Body Material	Nominal Total Delay (td)	Surface Mount	No. of Functions	No. of Taps/Steps	Technology	Programmable Delay Line	Nominal Supply Voltage / Vsup (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	Terminal Pitch	Maximum Operating Temperature	Minimum Operating Temperature	Terminal Finish	Terminal Position	JESD-30 Code	Maximum Supply Voltage (Vsup)	Qualification	Output Polarity	Minimum Supply Voltage (Vsup)	Maximum Power Supply Current (ICC)	Additional Features	JESD-609 Code	Family	Maximum Input Frequency (fmax)
DS1007(DIE)-6	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	20 ns	YES	7	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V		7 INDEPENDENT BUFFERED DELAYS DELAY[NS] = 6,6,6,6,20,20,20	e0	CMOS/TTL	16.6667 MHz
DS1000-150	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	150 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0	CMOS/TTL	4.16667 MHz
DS1007(DIE)-9	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	35 ns	YES	7	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V		7 INDEPENDENT BUFFERED DELAYS DELAY[NS] = 9,9,9,9,35,35,35	e0	CMOS/TTL	9.52381 MHz
DS1000-30	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	30 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0	CMOS/TTL	20.8333 MHz
DS1040(DIE)-D70	Maxim Integrated	PULSE GENERATOR DELAY LINE	COMMERCIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED		YES	1	5	CMOS	YES	5		UNCASED CHIP				70 Cel	0 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	COMPLEMENTARY	4.75 V		SILICON PULSE GENERATOR; PULSE WIDTH CHANGE PER STEP = 10NS	e0	CMOS/TTL	8.33333 MHz
DS1003-33	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	15.2 ns	YES	1	4	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V	110 mA	DELAY FROM INPUT TO 4 TAPS[NS] = 6,10.5,10.7,15.2; FOR RISC APPLICATIONS	e0	CMOS/TTL	71.43 MHz
DS1010(DIE)-200	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	200 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0	CMOS/TTL	3.125 MHz
DS1000-60	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	60 ns	YES	1	5	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V	75 mA	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0	CMOS/TTL	10.4167 MHz
DS1012(DIE)-4	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	25 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V		DELAY TRAILING EDGE[TYP.] = +-1NS OVER LEADING EDGE DELAY	e0	CMOS/TTL	6.66667 MHz
DS1005(DIE)-200	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	200 ns	YES	1	5	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0	CMOS/TTL	3.125 MHz
DS1013(DIE)-35	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	35 ns	YES	3	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0	CMOS/TTL	9.52381 MHz
DS1003-25	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD	14	DIE	UNSPECIFIED	UNSPECIFIED	20.2 ns	YES	1	4	CMOS	NO	5	5	UNCASED CHIP	DIP14,.3	Delay Lines	2.54 mm	85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V	95 mA	DELAY FROM INPUT TO 4 TAPS[NS] = 8,14,14.2,20.2; MAX FAN OUT OF 4 LSTTL/CMOS LOAD PER OUTPUT	e0	CMOS/TTL	52.63 MHz
DS1012(DIE)-V20	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	50 ns	YES	2	1	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V		TWO INDEPENDENT BUFFERED DELAYS PER INPUT; OUT3 = D3 NAND D4, OUT4 = D3 NOR D4	e0	CMOS/TTL	3.33333 MHz
DS1010(DIE)-80	Maxim Integrated	SILICON DELAY LINE	INDUSTRIAL	NO LEAD		DIE	UNSPECIFIED	UNSPECIFIED	80 ns	YES	1	10	CMOS	NO	5		UNCASED CHIP				85 Cel	-40 Cel	TIN LEAD	UPPER	X-XUUC-N	5.25 V	Not Qualified	TRUE	4.75 V		BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT	e0	CMOS/TTL	7.8125 MHz

Delay Lines

A delay line is an electronic component used in digital systems to introduce a delay or a time lag in a signal. Delay lines are commonly used in digital systems that require precise timing, synchronization, or control of signals.

Delay lines can be passive or active, depending on the method used to introduce the delay in the signal. Passive delay lines use passive components, such as capacitors, inductors, and resistors, to introduce the delay in the signal. Active delay lines use active components, such as amplifiers, to introduce the delay in the signal.

Delay lines can also be fixed or variable, depending on whether the delay introduced in the signal is fixed or can be adjusted. Fixed delay lines introduce a fixed delay in the signal, while variable delay lines can be adjusted to introduce a variable delay in the signal.

Delay lines are often used in digital systems that require precise timing or synchronization between different components or devices. For example, in a memory system, a delay line may be used to ensure that the signals sent to and received from the memory chips are synchronized and aligned with the clock signal.

Delay lines can also be used to compensate for signal propagation delays caused by long transmission lines or cables. In this case, the delay line is used to introduce a delay in the signal to compensate for the delay caused by the transmission line or cable.