Part | RoHS | Manufacturer | Programmable IC Type | Grading Of Temperature | Form Of Terminal | No. of Terminals | Package Code | Package Shape | Total Dose (V) | Package Body Material | No. of Logic Cells | Surface Mount | Maximum Supply Voltage | No. of CLBs | Technology Used | Screening Level | No. of Inputs | No. of Equivalent Gates | Nominal Supply Voltage (V) | Packing Method | Power Supplies (V) | Package Style (Meter) | Package Equivalence Code | Sub-Category | Minimum Supply Voltage | Pitch Of Terminal | Maximum Operating Temperature | Maximum Combinatorial Delay of a CLB | Organization | Minimum Operating Temperature | Finishing Of Terminal Used | Position Of Terminal | JESD-30 Code | Moisture Sensitivity Level (MSL) | Maximum Seated Height | Width | Qualification | Additional Features | JESD-609 Code | Maximum Clock Frequency | Maximum Time At Peak Reflow Temperature (s) | No. of Outputs | Peak Reflow Temperature (C) | Length |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
6000 |
5 |
Grid Array |
4.5 V |
125 °C (257 °F) |
6000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
No |
||||||||||||||||||||||||
Texas Instruments |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
8000 |
5 |
Grid Array |
4.5 V |
125 °C (257 °F) |
8000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
No |
||||||||||||||||||||||||
Xilinx |
FPGA |
Pin/Peg |
120 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.5 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array, Heat Sink/Slug |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
2.7 ns |
100 CLBS, 2000 Gates |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
Max usable 3000 Logic gates |
111 MHz |
80 |
34.544 mm |
|||||||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
100 |
CMOS |
2000 |
5 |
Grid Array |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e3 |
166 MHz |
34.544 mm |
|||||||||||||||
|
Xilinx |
FPGA |
Industrial |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.5 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
85 °C (185 °F) |
6 ns |
100 CLBS, 2500 Gates |
-40 °C (-40 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
90.9 MHz |
80 |
34.544 mm |
|||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
CMOS |
MIL-STD-883 |
80 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Gold |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e4 |
50 MHz |
80 |
34.544 mm |
||||||||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.25 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array, Heat Sink/Slug |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
2 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
Max usable 3000 Logic gates |
125 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Industrial |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
No |
5.5 V |
144 |
CMOS |
95 |
3200 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
85 °C (185 °F) |
6 ns |
144 CLBS, 3200 Gates |
-40 °C (-40 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
480 flip-flops; typical gates = 3200-4000 |
90.9 MHz |
95 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Pin/Peg |
120 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.5 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array, Heat Sink/Slug |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
2 ns |
100 CLBS, 2000 Gates |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
Max usable 3000 Logic gates |
125 MHz |
80 |
34.544 mm |
||||||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic |
238 |
No |
CMOS |
38535Q/M;38534H;883B |
80 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Perpendicular |
S-XPGA-P120 |
No |
90.9 MHz |
80 |
||||||||||||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
100 |
CMOS |
2000 |
5 |
Grid Array |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e3 |
125 MHz |
34.544 mm |
|||||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.5 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
166 MHz |
80 |
34.544 mm |
||||||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.5 V |
100 |
CMOS |
MIL-STD-883 Class B |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
125 °C (257 °F) |
6 ns |
100 CLBS, 2500 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
90.9 MHz |
80 |
34.544 mm |
||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.25 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array, Heat Sink/Slug |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
2.7 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
Max usable 3000 Logic gates |
111 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
No |
5.25 V |
144 |
CMOS |
95 |
3200 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
4.5 ns |
144 CLBS, 3200 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
480 flip-flops; typical gates = 3200-4000 |
133.3 MHz |
95 |
34.544 mm |
|||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.5 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
125 MHz |
80 |
34.544 mm |
||||||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
100 |
CMOS |
2000 |
5 |
Grid Array |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e3 |
111 MHz |
34.544 mm |
|||||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
CMOS |
MIL-STD-883 |
5 |
Grid Array |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Gold |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e4 |
34.544 mm |
|||||||||||||||||||||
|
Xilinx |
FPGA |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.5 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
100 CLBS, 2000 Gates |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e0 |
166 MHz |
80 |
34.544 mm |
|||||||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
No |
5.25 V |
144 |
CMOS |
95 |
3200 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
6 ns |
144 CLBS, 3200 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
480 flip-flops; typical gates = 3200-4000 |
90.9 MHz |
95 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.25 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array, Heat Sink/Slug |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
1.6 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
Max usable 3000 Logic gates |
125 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.25 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
4 ns |
100 CLBS, 2500 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
133.3 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.25 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
4.5 ns |
100 CLBS, 2500 Gates |
0 °C (32 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
e3 |
133.3 MHz |
80 |
34.544 mm |
|||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.5 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
125 MHz |
80 |
34.544 mm |
||||||||||||
|
Xilinx |
FPGA |
Pin/Peg |
120 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.5 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array, Heat Sink/Slug |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
1.6 ns |
100 CLBS, 2000 Gates |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
Max usable 3000 Logic gates |
125 MHz |
80 |
34.544 mm |
||||||||||||
|
Xilinx |
FPGA |
Industrial |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.5 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
85 °C (185 °F) |
6 ns |
100 CLBS, 2500 Gates |
-40 °C (-40 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
90.9 MHz |
80 |
34.544 mm |
|||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
100 |
CMOS |
MIL-STD-883 Class B |
2500 |
5 |
Grid Array |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2500 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
34.544 mm |
|||||||||||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic |
238 |
No |
CMOS |
80 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Perpendicular |
S-XPGA-P120 |
No |
90.9 MHz |
80 |
|||||||||||||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.25 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
4.5 ns |
100 CLBS, 2500 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
133.3 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.25 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
4 ns |
100 CLBS, 2500 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
133.3 MHz |
80 |
34.544 mm |
|||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
CMOS |
MIL-STD-883 |
80 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
2.54 mm |
125 °C (257 °F) |
6 ns |
-55 °C (-67 °F) |
Gold |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e4 |
90.9 MHz |
80 |
34.544 mm |
|||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
100 |
CMOS |
2500 |
5 |
Grid Array |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2500 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
34.544 mm |
||||||||||||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
No |
5.25 V |
144 |
CMOS |
95 |
3200 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
4 ns |
144 CLBS, 3200 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
MAX 96 I/OS; 480 flip-flops; typical gates = 3200 - 4000 |
133.3 MHz |
95 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
100 |
No |
5.25 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Grid Array, Heat Sink/Slug |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
1.3 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
Max usable 3000 Logic gates |
166 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.25 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
6 ns |
100 CLBS, 2500 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
90.9 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
100 |
CMOS |
2000 |
5 |
Grid Array |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e3 |
125 MHz |
34.544 mm |
|||||||||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.5 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
125 °C (257 °F) |
6 ns |
100 CLBS, 2500 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
90.9 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
152 |
No |
5.25 V |
64 |
CMOS |
80 |
1600 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
6 ns |
64 CLBS, 1600 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
256 flip-flops; typical gates = 1600-2000 |
90.9 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
238 |
No |
5.25 V |
100 |
CMOS |
80 |
2500 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
6 ns |
100 CLBS, 2500 Gates |
0 °C (32 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
360 flip-flops; typical gates = 2500-3000 |
e3 |
90.9 MHz |
80 |
34.544 mm |
|||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
152 |
No |
5.25 V |
64 |
CMOS |
80 |
1600 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
4.5 ns |
64 CLBS, 1600 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
256 flip-flops; typical gates = 1600-2000 |
133.3 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Industrial |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
152 |
No |
5.5 V |
64 |
CMOS |
80 |
1600 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
85 °C (185 °F) |
6 ns |
64 CLBS, 1600 Gates |
-40 °C (-40 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
256 flip-flops; typical gates = 1600-2000 |
90.9 MHz |
80 |
34.544 mm |
|||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
152 |
No |
5.25 V |
64 |
CMOS |
80 |
1600 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
4 ns |
64 CLBS, 1600 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
MAX 64 I/OS; 256 flip-flops; typical gates = 1600 - 2000 |
133.3 MHz |
80 |
34.544 mm |
|||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
100 |
CMOS |
2000 |
5 |
Grid Array |
4.5 V |
2.54 mm |
125 °C (257 °F) |
100 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
111 MHz |
34.544 mm |
||||||||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
CMOS |
MIL-STD-883 |
5 |
Grid Array |
2.54 mm |
125 °C (257 °F) |
6 ns |
-55 °C (-67 °F) |
Gold |
Perpendicular |
S-CPGA-P120 |
4.318 mm |
34.544 mm |
No |
e4 |
34.544 mm |
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits that are programmable by the user to perform specific logic functions. They consist of a matrix of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes FPGAs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.
FPGAs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the FPGA hardware. The resulting configuration data is then loaded onto the FPGA, allowing it to perform the desired logic functions.
FPGAs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.