Part | RoHS | Manufacturer | Programmable IC Type | Grading Of Temperature | Form Of Terminal | No. of Terminals | Package Code | Package Shape | Total Dose (V) | Package Body Material | No. of Logic Cells | Surface Mount | Maximum Supply Voltage | No. of CLBs | Technology Used | Screening Level | No. of Inputs | No. of Equivalent Gates | Nominal Supply Voltage (V) | Packing Method | Power Supplies (V) | Package Style (Meter) | Package Equivalence Code | Sub-Category | Minimum Supply Voltage | Pitch Of Terminal | Maximum Operating Temperature | Maximum Combinatorial Delay of a CLB | Organization | Minimum Operating Temperature | Finishing Of Terminal Used | Position Of Terminal | JESD-30 Code | Moisture Sensitivity Level (MSL) | Maximum Seated Height | Width | Qualification | Additional Features | JESD-609 Code | Maximum Clock Frequency | Maximum Time At Peak Reflow Temperature (s) | No. of Outputs | Peak Reflow Temperature (C) | Length |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Xilinx |
FPGA |
Pin/Peg |
475 |
PGA |
Square |
Ceramic |
2304 |
No |
CMOS |
384 |
3.3 |
3.3 V |
Grid Array |
SPGA475,41X41 |
Field Programmable Gate Arrays |
1.27 mm |
Perpendicular |
S-XPGA-P475 |
No |
e0 |
217 MHz |
384 |
|||||||||||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
5472 |
No |
3.6 V |
2304 |
CMOS |
MIL-PRF-38535 Class Q |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
125 °C (257 °F) |
1.6 ns |
2304 CLBS, 40000 Gates |
-55 °C (-67 °F) |
Gold |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
e4 |
166 MHz |
384 |
54.864 mm |
||||||||
|
Xilinx |
FPGA |
Pin/Peg |
475 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
2304 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
1.3 ns |
2304 CLBS, 40000 Gates |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Max usable 62000 Logic gates |
200 MHz |
384 |
54.864 mm |
||||||||||||
|
Xilinx |
FPGA |
Pin/Peg |
475 |
PGA |
Square |
Ceramic |
2304 |
No |
CMOS |
384 |
3.3 |
3.3 V |
Grid Array |
SPGA475,41X41 |
Field Programmable Gate Arrays |
1.27 mm |
Perpendicular |
S-XPGA-P475 |
No |
e0 |
238 MHz |
384 |
|||||||||||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
3.6 V |
2304 |
CMOS |
40000 |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
3 V |
2.54 mm |
125 °C (257 °F) |
2304 CLBS, 40000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P475 |
5.334 mm |
54.864 mm |
No |
Can also use 130000 gates |
54.864 mm |
||||||||||||||||||
Xilinx |
FPGA |
Other |
Pin/Peg |
475 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
5472 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
85 °C (185 °F) |
1.1 ns |
2304 CLBS, 40000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Max usable 62000 Logic gates |
238 MHz |
384 |
54.864 mm |
||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
3.6 V |
3136 |
CMOS |
MIL-PRF-38535 Class Q |
55000 |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
3 V |
2.54 mm |
125 °C (257 °F) |
1.3 ns |
3136 CLBS, 55000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
200 MHz |
54.864 mm |
||||||||||||||||
Xilinx |
FPGA |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.25 V |
2304 |
CMOS |
40000 |
5 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
4.75 V |
2.54 mm |
2304 CLBS, 40000 Gates |
Perpendicular |
S-CPGA-P475 |
5.334 mm |
54.864 mm |
No |
Typical gates = 40000-130000 |
54.864 mm |
|||||||||||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
3.6 V |
3136 |
CMOS |
MIL-PRF-38535 Class Q |
55000 |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
3 V |
2.54 mm |
125 °C (257 °F) |
1.3 ns |
3136 CLBS, 55000 Gates |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
e0 |
200 MHz |
54.864 mm |
||||||||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
2304 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
85 °C (185 °F) |
1.1 ns |
2304 CLBS, 40000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Typical gates = 40000-130000 |
238 MHz |
384 |
54.864 mm |
|||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
3.6 V |
3136 |
CMOS |
MIL-PRF-38535 |
55000 |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
3 V |
2.54 mm |
125 °C (257 °F) |
1.3 ns |
3136 CLBS, 55000 Gates |
-55 °C (-67 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Typical gates = 55000 to 180000 |
e3 |
200 MHz |
54.864 mm |
||||||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
475 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
2304 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
85 °C (185 °F) |
1.3 ns |
2304 CLBS, 40000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Max usable 62000 Logic gates |
200 MHz |
384 |
54.864 mm |
|||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
3.6 V |
2304 |
CMOS |
MIL-PRF-38535 Class Q |
40000 |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
3 V |
2.54 mm |
125 °C (257 °F) |
1.6 ns |
2304 CLBS, 40000 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
166 MHz |
54.864 mm |
||||||||||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
475 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
2304 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
85 °C (185 °F) |
1.5 ns |
2304 CLBS, 40000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Max usable 62000 Logic gates |
179 MHz |
384 |
54.864 mm |
|||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
3.6 V |
2304 |
CMOS |
MIL-PRF-38535 Class Q |
40000 |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
3 V |
2.54 mm |
125 °C (257 °F) |
1.6 ns |
2304 CLBS, 40000 Gates |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
e0 |
166 MHz |
54.864 mm |
||||||||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
5472 |
No |
3.6 V |
2304 |
CMOS |
MIL-PRF-38535 |
352 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
125 °C (257 °F) |
1.6 ns |
2304 CLBS, 40000 Gates |
-55 °C (-67 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Typical gates = 40000 to 130000 |
e3 |
166 MHz |
352 |
54.864 mm |
||||||
Xilinx |
FPGA |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
CMOS |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
2.54 mm |
Matte Tin |
Perpendicular |
S-CPGA-P475 |
5.334 mm |
54.864 mm |
No |
e3 |
54.864 mm |
|||||||||||||||||||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
475 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
2304 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
85 °C (185 °F) |
1.6 ns |
2304 CLBS, 40000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Max usable 62000 Logic gates |
166 MHz |
384 |
54.864 mm |
|||||||||
Xilinx |
FPGA |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
CMOS |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
2.54 mm |
Matte Tin |
Perpendicular |
S-CPGA-P475 |
5.334 mm |
54.864 mm |
No |
e3 |
54.864 mm |
|||||||||||||||||||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
2304 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
85 °C (185 °F) |
1.2 ns |
2304 CLBS, 40000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Typical gates = 40000-130000 |
217 MHz |
384 |
54.864 mm |
|||||||||
Xilinx |
FPGA |
Other |
Pin/Peg |
475 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
5472 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
85 °C (185 °F) |
1.2 ns |
2304 CLBS, 40000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Max usable 62000 Logic gates |
217 MHz |
384 |
54.864 mm |
||||||||||
|
Xilinx |
FPGA |
Pin/Peg |
475 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
2304 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
1.5 ns |
2304 CLBS, 40000 Gates |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Max usable 62000 Logic gates |
179 MHz |
384 |
54.864 mm |
||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
3.6 V |
3136 |
CMOS |
MIL-PRF-38535 Class Q |
55000 |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
3 V |
2.54 mm |
125 °C (257 °F) |
1.3 ns |
3136 CLBS, 55000 Gates |
-55 °C (-67 °F) |
Gold |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
e4 |
200 MHz |
54.864 mm |
||||||||||||||
Xilinx |
FPGA |
Military |
Pin/Peg |
475 |
HIPGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
3.6 V |
3136 |
55000 |
3.3 |
Grid Array, Heat Sink/Slug, Interstitial Pitch |
3 V |
2.54 mm |
125 °C (257 °F) |
2.9 ns |
3136 CLBS, 55000 Gates |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Maximum usable gates 180000 |
e0 |
166 MHz |
54.864 mm |
|||||||||||||||
|
Xilinx |
FPGA |
Pin/Peg |
475 |
HPGA |
Square |
Ceramic, Metal-Sealed Cofired |
2304 |
No |
3.6 V |
2304 |
CMOS |
384 |
40000 |
3.3 |
3.3 V |
Grid Array, Heat Sink/Slug |
SPGA475,41X41 |
Field Programmable Gate Arrays |
3 V |
2.54 mm |
1.6 ns |
2304 CLBS, 40000 Gates |
Perpendicular |
S-CPGA-P475 |
5.969 mm |
54.864 mm |
No |
Max usable 62000 Logic gates |
166 MHz |
384 |
54.864 mm |
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits that are programmable by the user to perform specific logic functions. They consist of a matrix of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes FPGAs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.
FPGAs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the FPGA hardware. The resulting configuration data is then loaded onto the FPGA, allowing it to perform the desired logic functions.
FPGAs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.