672 Programmable Logic Devices (PLD) 351

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Part RoHS Manufacturer Programmable IC Type Grading Of Temperature Form Of Terminal No. of Terminals Package Code Package Shape Package Body Material Propagation Delay No. of Logic Cells Surface Mount Maximum Supply Voltage No. of Macro Cells Technology Used Screening Level No. of Inputs Architecture Nominal Supply Voltage (V) Packing Method Power Supplies (V) Package Style (Meter) Package Equivalence Code Sub-Category In-System Programmable Output Function Minimum Supply Voltage No. of Product Terms Pitch Of Terminal Maximum Operating Temperature Organization No. of Dedicated Inputs Minimum Operating Temperature Finishing Of Terminal Used Position Of Terminal JESD-30 Code Moisture Sensitivity Level (MSL) Maximum Seated Height Width Qualification Additional Features JESD-609 Code Maximum Clock Frequency Maximum Time At Peak Reflow Temperature (s) No. of Outputs Peak Reflow Temperature (C) Length JTAG Boundary Scan Test No. of I/O Lines

EPF10K50SFI672-3

Altera

Loadable PLD

Industrial

Ball

672

BGA

Square

Plastic/Epoxy

12.5 ns

2880

Yes

2.7 V

CMOS

254

2.5

2.5,2.5/3.3 V

Grid Array

BGA672,26X26,40

Field Programmable Gate Arrays

Mixed

2.3 V

1 mm

85 °C (185 °F)

254 I/O

-40 °C (-40 °F)

Tin Lead

Bottom

S-PBGA-B672

3

2.1 mm

27 mm

No

e0

254

220 °C (428 °F)

27 mm

254

EP20K100EFC672-3

Altera

Loadable PLD

Other

Ball

672

BGA

Square

Plastic/Epoxy

Yes

1.89 V

1.8

Grid Array

Macrocell

1.71 V

1 mm

85 °C (185 °F)

4 Dedicated Inputs, 246 I/O

4

0 °C (32 °F)

Tin Silver Copper

Bottom

S-PBGA-B672

3

2.1 mm

27 mm

No

e1

160 MHz

220 °C (428 °F)

27 mm

246

EP20K400EBC672-2

Altera

Loadable PLD

Other

Ball

672

BGA

Square

Plastic/Epoxy

Yes

1.8

Grid Array

Macrocell

85 °C (185 °F)

4 Dedicated Inputs, 488 I/O

4

0 °C (32 °F)

Tin Lead

Bottom

S-PBGA-B672

No

e0

488

EP20K200FI672-2

Altera

Loadable PLD

Ball

672

BGA

Square

Plastic/Epoxy

Yes

2.625 V

2.5

Grid Array

Macrocell

2.375 V

1 mm

4 Dedicated Inputs, 382 I/O

4

Tin Silver Copper

Bottom

S-PBGA-B672

3

2.1 mm

27 mm

No

e1

220 °C (428 °F)

27 mm

382

EP2A40F672C7

Altera

Loadable PLD

Other

Ball

672

BGA

Square

Plastic/Epoxy

1.55 ns

38400

Yes

1.575 V

CMOS

480

1.5

1.5,1.5/3.3 V

Grid Array

BGA672,26X26,40

Field Programmable Gate Arrays

Macrocell

1.425 V

1 mm

85 °C (185 °F)

492 I/O

0 °C (32 °F)

Tin Lead

Bottom

S-PBGA-B672

3

2.1 mm

27 mm

No

e0

480

220 °C (428 °F)

27 mm

492

EPF10K200EBI672-1

Altera

Loadable PLD

Industrial

Ball

672

BGA

Square

Plastic/Epoxy

0.4 ns

Yes

2.7 V

2.5

Grid Array

Mixed

2.3 V

85 °C (185 °F)

4 Dedicated Inputs, 470 I/O

4

-40 °C (-40 °F)

Tin Silver Copper

Bottom

S-PBGA-B672

No

e1

470

EPF10K200SFC672-1

Altera

Loadable PLD

Commercial

Ball

672

BGA

Square

Plastic/Epoxy

0.3 ns

9984

Yes

2.625 V

CMOS

470

2.5

2.5,2.5/3.3 V

Grid Array

BGA672,26X26,40

Field Programmable Gate Arrays

Mixed

2.375 V

1 mm

70 °C (158 °F)

470 I/O

0 °C (32 °F)

Tin Lead

Bottom

S-PBGA-B672

3

2.1 mm

27 mm

No

e0

470

220 °C (428 °F)

27 mm

470

EP2A25F672C7

Altera

Loadable PLD

Other

Ball

672

BGA

Square

Plastic/Epoxy

1.69 ns

24320

Yes

1.575 V

CMOS

480

1.5

1.5,1.5/3.3 V

Grid Array

BGA672,26X26,40

Field Programmable Gate Arrays

Macrocell

1.425 V

1 mm

85 °C (185 °F)

492 I/O

0 °C (32 °F)

Tin Lead

Bottom

S-PBGA-B672

3

2.1 mm

27 mm

No

e0

20 s

480

220 °C (428 °F)

27 mm

492

EPXA4F672I2

Altera

Loadable PLD

Ball

672

BGA

Square

Plastic/Epoxy

Yes

1.89 V

1.8

Grid Array

Macrocell

1.71 V

1 mm

0 Dedicated Inputs, 426 I/O

0

Tin Lead

Bottom

S-PBGA-B672

3

2.1 mm

27 mm

No

e0

220 °C (428 °F)

27 mm

426

EP20K400EFC672-1X

Altera

Loadable PLD

Other

Ball

672

BGA

Square

Plastic/Epoxy

1.57 ns

16640

Yes

1.89 V

CMOS

480

1.8

1.8,1.8/3.3 V

Grid Array

BGA672,26X26,40

Field Programmable Gate Arrays

Macrocell

1.71 V

1 mm

85 °C (185 °F)

4 Dedicated Inputs, 488 I/O

4

0 °C (32 °F)

Tin Lead

Bottom

S-PBGA-B672

3

3.5 mm

27 mm

No

e0

160 MHz

20 s

480

220 °C (428 °F)

27 mm

488

EP20K600EFC672-2X

Altera

Loadable PLD

Other

Ball

672

BGA

Square

Plastic/Epoxy

2.25 ns

24320

Yes

1.89 V

CMOS

500

1.8

1.8,1.8/3.3 V

Grid Array

BGA672,26X26,40

Field Programmable Gate Arrays

Macrocell

1.71 V

1 mm

85 °C (185 °F)

4 Dedicated Inputs, 508 I/O

4

0 °C (32 °F)

Tin Lead

Bottom

S-PBGA-B672

3

3.5 mm

27 mm

No

e0

160 MHz

20 s

500

220 °C (428 °F)

27 mm

508

EPF10K130EFC672-1X

Altera

Loadable PLD

Commercial

Ball

672

BGA

Square

Plastic/Epoxy

0.3 ns

6656

Yes

2.625 V

CMOS

413

2.5

2.5,2.5/3.3 V

Grid Array

BGA672,26X26,40

Field Programmable Gate Arrays

Mixed

2.375 V

1 mm

70 °C (158 °F)

413 I/O

0 °C (32 °F)

Tin Lead

Bottom

S-PBGA-B672

3

2.1 mm

27 mm

No

e0

413

220 °C (428 °F)

27 mm

413

EP20K1000EFC672-2

Altera

Loadable PLD

Other

Ball

672

BGA

Square

Plastic/Epoxy

2.13 ns

38400

Yes

1.89 V

CMOS

500

1.8

1.8,1.8/3.3 V

Grid Array

BGA672,26X26,40

Field Programmable Gate Arrays

Macrocell

1.71 V

1 mm

85 °C (185 °F)

4 Dedicated Inputs, 508 I/O

4

0 °C (32 °F)

Tin Lead

Bottom

S-PBGA-B672

3

3.5 mm

27 mm

No

e0

160 MHz

20 s

500

220 °C (428 °F)

27 mm

508

EPF10K100EBC672-2

Altera

Loadable PLD

Commercial

Ball

672

BGA

Square

Plastic/Epoxy

0.7 ns

Yes

2.7 V

2.5

Grid Array

Mixed

2.3 V

70 °C (158 °F)

4 Dedicated Inputs, 338 I/O

4

0 °C (32 °F)

Tin Silver Copper

Bottom

S-PBGA-B672

No

e1

338

EPF10K30EBC672-3

Altera

Loadable PLD

Commercial

Ball

672

BGA

Square

Plastic/Epoxy

0.9 ns

Yes

2.7 V

2.5

Grid Array

Mixed

2.3 V

70 °C (158 °F)

4 Dedicated Inputs, 220 I/O

4

0 °C (32 °F)

Tin Silver Copper

Bottom

S-PBGA-B672

No

e1

220

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.