Mask PLD Programmable Logic Devices (PLD) 118

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	Technology Used	Nominal Supply Voltage (V)	Package Style (Meter)	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Peak Reflow Temperature (C)	Length	No. of I/O Lines
MPM5064LC-1	Altera	Mask PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	40 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 28 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No	Labs interconnected by PIA; 4 Labs; 64 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz	220 °C (428 °F)	16.5862 mm	28
MPM5192QC	Altera	Mask PLD	Commercial	Gull Wing	100	QFP	Rectangular	Plastic/Epoxy	55 ns	Yes	5.25 V	CMOS	5	Flatpack	Macrocell	4.75 V	.65 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Matte Tin	Quad	R-PQFP-G100	3	3.13 mm	13.2 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e3	33.3 MHz	220 °C (428 °F)	20 mm	64
MPM5128LC-1	Altera	Mask PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz	220 °C (428 °F)	24.2316 mm	52
MPM1810LC-35	Altera	Mask PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)		Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	48 Macrocells; 4 External Clocks; Shared Input/Clock		28.6 MHz		24.2316 mm	48
MPM5130QC	Altera	Mask PLD	Commercial	Gull Wing	100	QFP	Rectangular	Plastic/Epoxy	55 ns	Yes	5.25 V	CMOS	5	Flatpack	Macrocell	4.75 V	.65 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)	Matte Tin	Quad	R-PQFP-G100	3	3.13 mm	13.2 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e3	33.3 MHz	220 °C (428 °F)	20 mm	64
MPM5130GC	Altera	Mask PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.25 V	CMOS	5	Grid Array, Window	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100	1	4.953 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz	220 °C (428 °F)	33.528 mm	64
MPM5130QC-2	Altera	Mask PLD	Commercial	Gull Wing	100	QFP	Rectangular	Plastic/Epoxy	45 ns	Yes	5.25 V	CMOS	5	Flatpack	Macrocell	4.75 V	.65 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)	Matte Tin	Quad	R-PQFP-G100	3	3.13 mm	13.2 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e3	40 MHz	220 °C (428 °F)	20 mm	64
MPM5064LC	Altera	Mask PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	55 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 28 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No	Labs interconnected by PIA; 4 Labs; 64 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz	220 °C (428 °F)	16.5862 mm	28
MPM5192LC-2	Altera	Mask PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	45 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J84		4.572 mm	29.3116 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz	220 °C (428 °F)	29.3116 mm	64
MPM5032PC-25	Altera	Mask PLD	Commercial	Through-Hole	28	DIP	Rectangular	Plastic/Epoxy	25 ns	No	5.25 V	CMOS	5	In-Line	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 16 I/O	7	0 °C (32 °F)		Dual	R-PDIP-T28		4.318 mm	7.62 mm	No	Macrocells interconnected by PIA; 1 LAB; 32 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz	220 °C (428 °F)	34.29 mm	16
MPM5192QC-1	Altera	Mask PLD	Commercial	Gull Wing	100	QFP	Rectangular	Plastic/Epoxy	40 ns	Yes	5.25 V	CMOS	5	Flatpack	Macrocell	4.75 V	.65 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Matte Tin	Quad	R-PQFP-G100	3	3.13 mm	13.2 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e3	50 MHz	220 °C (428 °F)	20 mm	64
MPM5130GC-2	Altera	Mask PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.25 V	CMOS	5	Grid Array, Window	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100	1	4.953 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz	220 °C (428 °F)	33.528 mm	64
MPM5032LC-20	Altera	Mask PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	20 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 16 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No	Macrocells interconnected by PIA; 1 LAB; 32 Macrocells; 1 External Clock; Shared Input/Clock		62.5 MHz	220 °C (428 °F)	11.5062 mm	16
MPM5064LC-2	Altera	Mask PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	45 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 28 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No	Labs interconnected by PIA; 4 Labs; 64 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz	220 °C (428 °F)	16.5862 mm	28
MPM1810LC-25	Altera	Mask PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)		Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	48 Macrocells; 4 External Clocks; Shared Input/Clock		40 MHz		24.2316 mm	48
MPM5192QC-2	Altera	Mask PLD	Commercial	Gull Wing	100	QFP	Rectangular	Plastic/Epoxy	45 ns	Yes	5.25 V	CMOS	5	Flatpack	Macrocell	4.75 V	.65 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Matte Tin	Quad	R-PQFP-G100	3	3.13 mm	13.2 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e3	40 MHz	220 °C (428 °F)	20 mm	64
MPM5128LC	Altera	Mask PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	55 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz	220 °C (428 °F)	24.2316 mm	52
MPS464LC-20	Altera	Mask PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	20 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 32 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No	Macrocells Interconnected By Global Bus; Synchronous Timing Generator; 64 Macrocells	e0	66.7 MHz	220 °C (428 °F)	16.5862 mm	32
MPM5130GC-1	Altera	Mask PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.25 V	CMOS	5	Grid Array, Window	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100	1	4.953 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz	220 °C (428 °F)	33.528 mm	64
MPM5032LC-25	Altera	Mask PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	25 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 16 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No	Macrocells interconnected by PIA; 1 LAB; 32 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz	220 °C (428 °F)	11.5062 mm	16
MPM5130QC-1	Altera	Mask PLD	Commercial	Gull Wing	100	QFP	Rectangular	Plastic/Epoxy	40 ns	Yes	5.25 V	CMOS	5	Flatpack	Macrocell	4.75 V	.65 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)	Matte Tin	Quad	R-PQFP-G100	3	3.13 mm	13.2 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e3	50 MHz	220 °C (428 °F)	20 mm	64
MPS464LC-25	Altera	Mask PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	25 ns	Yes	5.25 V	CMOS	5	Chip Carrier	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 32 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No	Macrocells Interconnected By Global Bus; Synchronous Timing Generator; 64 Macrocells	e0	50 MHz	220 °C (428 °F)	16.5862 mm	32

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.