Analog Devices Programmable Logic Devices (PLD) 17

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Part RoHS Manufacturer Programmable IC Type Grading Of Temperature Form Of Terminal No. of Terminals Package Code Package Shape Package Body Material Propagation Delay No. of Logic Cells Surface Mount Maximum Supply Voltage No. of Macro Cells Technology Used Screening Level No. of Inputs Architecture Nominal Supply Voltage (V) Packing Method Power Supplies (V) Package Style (Meter) Package Equivalence Code Sub-Category In-System Programmable Output Function Minimum Supply Voltage No. of Product Terms Pitch Of Terminal Maximum Operating Temperature Organization No. of Dedicated Inputs Minimum Operating Temperature Finishing Of Terminal Used Position Of Terminal JESD-30 Code Moisture Sensitivity Level (MSL) Maximum Seated Height Width Qualification Additional Features JESD-609 Code Maximum Clock Frequency Maximum Time At Peak Reflow Temperature (s) No. of Outputs Peak Reflow Temperature (C) Length JTAG Boundary Scan Test No. of I/O Lines

MACH210AQ-15JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

15 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

50 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210-15JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

15 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

50 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210-18JI

Analog Devices

EE PLD

Industrial

J Bend

44

QCCJ

Square

Plastic/Epoxy

18 ns

Yes

5.5 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

4 Dedicated Inputs, 32 I/O

4

-40 °C (-40 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

40 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210A-12JI

Analog Devices

EE PLD

Industrial

J Bend

44

QCCJ

Square

Plastic/Epoxy

12 ns

Yes

5.5 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

4 Dedicated Inputs, 32 I/O

4

-40 °C (-40 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

64 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210A-7JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

7.5 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

100 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210AQ-20JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

20 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

40 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210-12JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

12 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

66.7 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210A-14JI

Analog Devices

EE PLD

Industrial

J Bend

44

QCCJ

Square

Plastic/Epoxy

14.5 ns

Yes

5.5 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

4 Dedicated Inputs, 32 I/O

4

-40 °C (-40 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

53 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210-20JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

20 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

40 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210A-12JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

12 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

66.7 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210AQ-12JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

12 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

66.7 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210A-10VC

Analog Devices

EE PLD

Commercial

Gull Wing

44

TQFP

Square

Plastic/Epoxy

10 ns

Yes

5.25 V

64

CMOS

5

5 V

Flatpack, Thin Profile

TQFP44,.47SQ,32

Programmable Logic Devices

No

Macrocell

4.75 V

.8 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQFP-G44

3

1.2 mm

10 mm

No

e0

80 MHz

240 °C (464 °F)

10 mm

No

32

MACH210A-12VC

Analog Devices

EE PLD

Commercial

Gull Wing

44

TQFP

Square

Plastic/Epoxy

12 ns

Yes

5.25 V

64

CMOS

5

5 V

Flatpack, Thin Profile

TQFP44,.47SQ,32

Programmable Logic Devices

No

Macrocell

4.75 V

.8 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQFP-G44

3

1.2 mm

10 mm

No

e0

66.7 MHz

240 °C (464 °F)

10 mm

No

32

MACH210A-10JC

Analog Devices

EE PLD

Commercial

J Bend

44

QCCJ

Square

Plastic/Epoxy

10 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

80 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210-24JI

Analog Devices

EE PLD

Industrial

J Bend

44

QCCJ

Square

Plastic/Epoxy

24 ns

Yes

5.5 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

4 Dedicated Inputs, 32 I/O

4

-40 °C (-40 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

32 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210-14JI

Analog Devices

EE PLD

Industrial

J Bend

44

QCCJ

Square

Plastic/Epoxy

14.5 ns

Yes

5.5 V

64

CMOS

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

4 Dedicated Inputs, 32 I/O

4

-40 °C (-40 °F)

Tin Lead

Quad

S-PQCC-J44

3

4.57 mm

16.5862 mm

No

e0

53 MHz

30 s

225 °C (437 °F)

16.5862 mm

No

32

MACH210A-7VC

Analog Devices

EE PLD

Commercial

Gull Wing

44

TQFP

Square

Plastic/Epoxy

7.5 ns

Yes

5.25 V

64

CMOS

5

5 V

Flatpack, Thin Profile

TQFP44,.47SQ,32

Programmable Logic Devices

No

Macrocell

4.75 V

.8 mm

70 °C (158 °F)

4 Dedicated Inputs, 32 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-PQFP-G44

3

1.2 mm

10 mm

No

e0

100 MHz

240 °C (464 °F)

10 mm

No

32

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.