
Image shown is a representation only.
Manufacturer | Altera |
---|---|
Manufacturer's Part Number | EP1810GC-25 |
Description | UV PLD; Grading Of Temperature: COMMERCIAL; Form Of Terminal: PIN/PEG; No. of Terminals: 68; Package Code: PGA; Package Shape: SQUARE; |
Datasheet | EP1810GC-25 Datasheet |
In Stock | 565 |
NAME | DESCRIPTION |
---|---|
Minimum Supply Voltage: | 4.75 V |
Package Body Material: | Ceramic, Metal-Sealed Cofired |
Propagation Delay: | 28 ns |
Organization: | 12 Dedicated Inputs, 48 I/O |
Sub-Category: | Programmable Logic Devices |
Surface Mount: | No |
Position Of Terminal: | Perpendicular |
No. of Terminals: | 68 |
JTAG Boundary Scan Test: | No |
No. of I/O Lines: | 48 |
Package Style (Meter): | Grid Array |
JESD-30 Code: | S-CPGA-P68 |
Maximum Clock Frequency: | 40 MHz |
Package Shape: | Square |
Maximum Operating Temperature: | 70 °C (158 °F) |
Package Code: | PGA |
No. of Dedicated Inputs: | 12 |
Moisture Sensitivity Level (MSL): | 1 |
Grading Of Temperature: | Commercial |
Programmable IC Type: | UV PLD |
Maximum Supply Voltage: | 5.25 V |
Nominal Supply Voltage (V): | 5 |
Technology Used: | CMOS |
JESD-609 Code: | e0 |
Minimum Operating Temperature: | 0 °C (32 °F) |
Qualification: | No |
Package Equivalence Code: | PGA68,11X11 |
Finishing Of Terminal Used: | Tin Lead |
Form Of Terminal: | Pin/Peg |
In-System Programmable: | No |
Additional Features: | Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks |
Output Function: | Macrocell |
Pitch Of Terminal: | 2.54 mm |
Peak Reflow Temperature (C): | 220 °C (428 °F) |
No. of Macro Cells: | 48 |
Power Supplies (V): | 5 V |