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| Manufacturer | Altera |
|---|---|
| Manufacturer's Part Number | EP20K400GI655-3 |
| Description | LOADABLE PLD; Form Of Terminal: PIN/PEG; No. of Terminals: 655; Package Code: IPGA; Package Shape: SQUARE; JESD-30 Code: S-CPGA-P655; |
| Datasheet | EP20K400GI655-3 Datasheet |
| In Stock | 257 |
| NAME | DESCRIPTION |
|---|---|
| Minimum Supply Voltage: | 2.375 V |
| Package Body Material: | Ceramic, Metal-Sealed Cofired |
| Organization: | 4 Dedicated Inputs, 502 I/O |
| Maximum Seated Height: | 4.08 mm |
| No. of Inputs: | 496 |
| Sub-Category: | Field Programmable Gate Arrays |
| Surface Mount: | No |
| No. of Outputs: | 496 |
| Position Of Terminal: | Perpendicular |
| No. of Terminals: | 655 |
| No. of I/O Lines: | 502 |
| Package Style (Meter): | Grid Array, Interstitial Pitch |
| JESD-30 Code: | S-CPGA-P655 |
| Package Shape: | Square |
| Package Code: | IPGA |
| Width: | 62.484 mm |
| No. of Dedicated Inputs: | 4 |
| Moisture Sensitivity Level (MSL): | 1 |
| Programmable IC Type: | Loadable PLD |
| Maximum Supply Voltage: | 2.625 V |
| Nominal Supply Voltage (V): | 2.5 |
| Technology Used: | CMOS |
| No. of Logic Cells: | 16640 |
| JESD-609 Code: | e0 |
| Qualification: | No |
| Package Equivalence Code: | SPGA655,47X47 |
| Finishing Of Terminal Used: | Tin Lead |
| Length: | 62.484 mm |
| Form Of Terminal: | Pin/Peg |
| Output Function: | Macrocell |
| Pitch Of Terminal: | 2.54 mm |
| Peak Reflow Temperature (C): | 220 °C (428 °F) |
| Power Supplies (V): | 2.5,2.5/3.3 V |









