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Manufacturer | Altera |
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Manufacturer's Part Number | EP910ADC-25 |
Description | UV PLD; Grading Of Temperature: COMMERCIAL; Form Of Terminal: THROUGH-HOLE; No. of Terminals: 40; Package Code: WDIP; Package Shape: RECTANGULAR; |
Datasheet | EP910ADC-25 Datasheet |
In Stock | 454 |
NAME | DESCRIPTION |
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Minimum Supply Voltage: | 4.75 V |
Package Body Material: | Ceramic, Glass-Sealed |
Propagation Delay: | 25 ns |
Organization: | 12 Dedicated Inputs, 24 I/O |
Maximum Seated Height: | 5.588 mm |
No. of Inputs: | 36 |
Sub-Category: | Programmable Logic Devices |
Surface Mount: | No |
No. of Outputs: | 24 |
Position Of Terminal: | Dual |
No. of Terminals: | 40 |
No. of I/O Lines: | 24 |
Package Style (Meter): | In-Line, Window |
JESD-30 Code: | R-GDIP-T40 |
Maximum Clock Frequency: | 40 MHz |
Package Shape: | Rectangular |
Maximum Operating Temperature: | 70 °C (158 °F) |
Package Code: | WDIP |
Width: | 15.24 mm |
No. of Dedicated Inputs: | 12 |
Grading Of Temperature: | Commercial |
Programmable IC Type: | UV PLD |
Maximum Supply Voltage: | 5.25 V |
Architecture: | PAL-TYPE |
No. of Product Terms: | 240 |
Nominal Supply Voltage (V): | 5 |
Technology Used: | CMOS |
JESD-609 Code: | e0 |
Minimum Operating Temperature: | 0 °C (32 °F) |
Qualification: | No |
Package Equivalence Code: | DIP40,.6 |
Finishing Of Terminal Used: | Tin Lead |
Length: | 52.07 mm |
Form Of Terminal: | Through-Hole |
Additional Features: | Macrocells Interconnected By Global Bus; 24 Macrocells; 2 External Clocks |
Output Function: | Macrocell |
Pitch Of Terminal: | 2.54 mm |
Peak Reflow Temperature (C): | 220 °C (428 °F) |
Power Supplies (V): | 5 V |