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Manufacturer | Altera |
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Manufacturer's Part Number | EPM5130GC-1 |
Description | UV PLD; Grading Of Temperature: COMMERCIAL; Form Of Terminal: PIN/PEG; No. of Terminals: 100; Package Code: PGA; Package Shape: SQUARE; |
Datasheet | EPM5130GC-1 Datasheet |
In Stock | 991 |
NAME | DESCRIPTION |
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Minimum Supply Voltage: | 4.75 V |
Package Body Material: | Ceramic, Metal-Sealed Cofired |
Propagation Delay: | 40 ns |
Organization: | 19 Dedicated Inputs, 64 I/O |
Sub-Category: | Programmable Logic Devices |
Surface Mount: | No |
Position Of Terminal: | Perpendicular |
No. of Terminals: | 100 |
JTAG Boundary Scan Test: | No |
No. of I/O Lines: | 64 |
Package Style (Meter): | Grid Array |
JESD-30 Code: | S-CPGA-P100 |
Maximum Clock Frequency: | 50 MHz |
Package Shape: | Square |
Maximum Operating Temperature: | 70 °C (158 °F) |
Package Code: | PGA |
No. of Dedicated Inputs: | 19 |
Moisture Sensitivity Level (MSL): | 1 |
Grading Of Temperature: | Commercial |
Programmable IC Type: | UV PLD |
Maximum Supply Voltage: | 5.25 V |
Nominal Supply Voltage (V): | 5 |
Technology Used: | CMOS |
JESD-609 Code: | e0 |
Minimum Operating Temperature: | 0 °C (32 °F) |
Qualification: | No |
Package Equivalence Code: | PGA100M,13X13 |
Finishing Of Terminal Used: | Tin Lead |
Form Of Terminal: | Pin/Peg |
In-System Programmable: | No |
Additional Features: | Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
Output Function: | Macrocell |
Pitch Of Terminal: | 2.54 mm |
Peak Reflow Temperature (C): | 220 °C (428 °F) |
No. of Macro Cells: | 128 |
Power Supplies (V): | 5 V |