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Manufacturer | Cypress Semiconductor |
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Manufacturer's Part Number | CY7C342-30HI |
Description | UV PLD; Grading Of Temperature: INDUSTRIAL; Form Of Terminal: J BEND; No. of Terminals: 68; Package Code: WQCCJ; Package Shape: SQUARE; |
Datasheet | CY7C342-30HI Datasheet |
NAME | DESCRIPTION |
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Minimum Supply Voltage: | 4.5 V |
Package Body Material: | Ceramic, Metal-Sealed Cofired |
Propagation Delay: | 60 ns |
Organization: | 7 Dedicated Inputs, 52 I/O |
Maximum Seated Height: | 5.08 mm |
Sub-Category: | Programmable Logic Devices |
Surface Mount: | Yes |
Position Of Terminal: | Quad |
No. of Terminals: | 68 |
JTAG Boundary Scan Test: | No |
No. of I/O Lines: | 52 |
Package Style (Meter): | Chip Carrier, Window |
JESD-30 Code: | S-CQCC-J68 |
Maximum Clock Frequency: | 27.7 MHz |
Package Shape: | Square |
Maximum Operating Temperature: | 85 °C (185 °F) |
Package Code: | WQCCJ |
Width: | 24.13 mm |
No. of Dedicated Inputs: | 7 |
Grading Of Temperature: | Industrial |
Programmable IC Type: | UV PLD |
Maximum Supply Voltage: | 5.5 V |
Nominal Supply Voltage (V): | 5 |
Technology Used: | CMOS |
JESD-609 Code: | e0 |
Minimum Operating Temperature: | -40 °C (-40 °F) |
Qualification: | No |
Package Equivalence Code: | LDCC68,1.0SQ |
Finishing Of Terminal Used: | Tin Lead |
Length: | 24.13 mm |
Form Of Terminal: | J Bend |
In-System Programmable: | No |
Additional Features: | Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
Output Function: | Macrocell |
Pitch Of Terminal: | 1.27 mm |
No. of Macro Cells: | 128 |
Power Supplies (V): | 5 V |