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Manufacturer | Xilinx |
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Manufacturer's Part Number | XC2064-50CD48I |
Description | FIELD PROGRAMMABLE GATE ARRAY; Grading Of Temperature: INDUSTRIAL; Form Of Terminal: THROUGH-HOLE; No. of Terminals: 48; Package Code: DIP; Package Shape: RECTANGULAR; |
Datasheet | XC2064-50CD48I Datasheet |
In Stock | 253 |
NAME | DESCRIPTION |
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Minimum Supply Voltage: | 4.5 V |
Package Body Material: | Ceramic, Metal-Sealed Cofired |
Organization: | 64 CLBS, 1200 Gates |
Maximum Combinatorial Delay of a CLB: | 15 ns |
Maximum Seated Height: | 9.271 mm |
No. of Inputs: | 40 |
Sub-Category: | Field Programmable Gate Arrays |
Surface Mount: | No |
No. of Outputs: | 40 |
Position Of Terminal: | Dual |
No. of Terminals: | 48 |
No. of Equivalent Gates: | 1200 |
Package Style (Meter): | In-Line |
JESD-30 Code: | R-CDIP-T48 |
Maximum Clock Frequency: | 50 MHz |
Package Shape: | Rectangular |
Maximum Operating Temperature: | 85 °C (185 °F) |
Package Code: | DIP |
Width: | 15.24 mm |
Moisture Sensitivity Level (MSL): | 1 |
Grading Of Temperature: | Industrial |
Programmable IC Type: | FPGA |
Maximum Supply Voltage: | 5.5 V |
Nominal Supply Voltage (V): | 5 |
Technology Used: | CMOS |
No. of Logic Cells: | 64 |
No. of CLBs: | 64 |
JESD-609 Code: | e0 |
Minimum Operating Temperature: | -40 °C (-40 °F) |
Qualification: | No |
Package Equivalence Code: | DIP48,.6 |
Finishing Of Terminal Used: | Tin Lead |
Length: | 60.96 mm |
Form Of Terminal: | Through-Hole |
Additional Features: | MAX 40 I/OS; 122 flip-flops |
Pitch Of Terminal: | 2.54 mm |
Power Supplies (V): | 5 V |