QCCJ Programmable Logic Devices (PLD) 2,131

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	No. of Logic Cells	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	No. of Inputs	Architecture	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	No. of Product Terms	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Maximum Time At Peak Reflow Temperature (s)	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EPF8282ALC84-4H	Altera	Loadable PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy			Yes	5.25 V		CMOS			5		Chip Carrier				Registered	4.75 V		1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 68 I/O	4	0 °C (32 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	208 Logic Elements						29.3116 mm		68
EP610LC28-30	Altera	OT PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	32 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)		Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No	16 Macrocells; 2 External Clocks		41.7 MHz				11.5062 mm		16
EPM7064LI84-15H	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 68 I/O	0	-40 °C (-40 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No			100 MHz				29.3116 mm		68
EPM7064SLC84-5	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	5 ns		Yes	5.25 V	64	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 68 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84	2	5.08 mm	29.3116 mm	No	64 Macrocells	e0	250 MHz	20 s		220 °C (428 °F)	29.3116 mm	Yes	68
EP1810LC68-45	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	50 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	48 Macrocells; Shared Input/Clock	e0	33.3 MHz			220 °C (428 °F)	24.2316 mm	No	48
EPM7096SLI68-15	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.5 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 48 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	76.9 MHz			220 °C (428 °F)	24.23 mm	No	48
EPM5130LC-2	Altera	OT PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	45 ns		Yes	5.25 V	128	CMOS			5	5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	19 Dedicated Inputs, 48 I/O	19	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84				No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz			220 °C (428 °F)		No	48
EPM5130LM	Altera	OT PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	55 ns		Yes	5.5 V	128	CMOS			5	5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	19 Dedicated Inputs, 48 I/O	19	-55 °C (-67 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz			220 °C (428 °F)	29.3116 mm	No	48
EPF8452ALI84-A-4	Altera	Loadable PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	1.9 ns		Yes	3.6 V		CMOS			3.3		Chip Carrier				Registered	3 V		1.27 mm	85 °C (185 °F)	4 Dedicated Inputs, 68 I/O	4	-40 °C (-40 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Can also operate at 5 V supply						29.3116 mm		68
EP610ILC-25	Altera	OT PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	25 ns		Yes	5.25 V		CMOS	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.75 V	160	1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J28		4.57 mm	11.505 mm	No		e0	40 MHz		16	220 °C (428 °F)	11.505 mm		16
EP910ILI-12	Altera	OT PLD	Industrial	J Bend	44	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.5 V		CMOS	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell	4.5 V	240	1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 24 I/O	12	-40 °C (-40 °F)	Tin/Lead	Quad	S-PQCC-J44		4.57 mm	16.585 mm	No	Macrocells Interconnected By Global Bus; 24 Macrocells; 2 External Clocks	e0	76.9 MHz	30 s	24	220 °C (428 °F)	16.585 mm		24
EP910JMB-40	Altera		Military	J Bend	44	QCCJ	Square	Ceramic	43 ns		Yes			CMOS	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell		240	1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-XQCC-J44						e0	25 MHz		24	220 °C (428 °F)
EP324LC-30	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	30 ns		Yes	5.25 V		CMOS	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell	4.75 V	394	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 24 I/O	8	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44				No	24 Macrocells	e0	50 MHz		24	220 °C (428 °F)			24
EP910ALC44-15	Altera	EE PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	16 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 24 I/O	12	0 °C (32 °F)		Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No	24 Macrocells; 2 External Clocks		71.4 MHz				16.5862 mm		24
EPX780LC84-15	Altera	OT PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	18 ns	80	Yes	5.25 V		CMOS	62		5	5 V	Chip Carrier	LDCC84,1.2SQ	Field Programmable Gate Arrays		Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 60 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	8 Labs; 80 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	50 MHz		62	220 °C (428 °F)	29.3116 mm		60
EPM5192LM84	Altera	OT PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	55 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz				29.3116 mm		64
EPM7096LC68-7	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	5.25 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	3	5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	166.7 MHz			220 °C (428 °F)	24.2316 mm	No	52
EP1810LM-45	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Plastic/Epoxy	50 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks		22.2 MHz				24.23 mm		48
EPM7160ELI84-10P	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	10 ns		Yes	5.5 V	160	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 60 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	100 MHz			220 °C (428 °F)	29.3116 mm	No	60

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.