WQCCJ Programmable Logic Devices (PLD) 257

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Part RoHS Manufacturer Programmable IC Type Grading Of Temperature Form Of Terminal No. of Terminals Package Code Package Shape Package Body Material Propagation Delay No. of Logic Cells Surface Mount Maximum Supply Voltage No. of Macro Cells Technology Used Screening Level No. of Inputs Architecture Nominal Supply Voltage (V) Packing Method Power Supplies (V) Package Style (Meter) Package Equivalence Code Sub-Category In-System Programmable Output Function Minimum Supply Voltage No. of Product Terms Pitch Of Terminal Maximum Operating Temperature Organization No. of Dedicated Inputs Minimum Operating Temperature Finishing Of Terminal Used Position Of Terminal JESD-30 Code Moisture Sensitivity Level (MSL) Maximum Seated Height Width Qualification Additional Features JESD-609 Code Maximum Clock Frequency Maximum Time At Peak Reflow Temperature (s) No. of Outputs Peak Reflow Temperature (C) Length JTAG Boundary Scan Test No. of I/O Lines

EP900JMB

Altera

UV PLD

Military

J Bend

44

WQCCJ

Square

Ceramic, Glass-Sealed

60 ns

Yes

5.5 V

CMOS

36

PAL-TYPE

5

5 V

Chip Carrier, Window

LDCC44,.7SQ

Programmable Logic Devices

Macrocell

4.5 V

240

1.27 mm

125 °C (257 °F)

12 Dedicated Inputs, 24 I/O

12

-55 °C (-67 °F)

Tin Lead

Quad

S-GQCC-J44

4.57 mm

16.51 mm

No

24 Macrocells

e0

20 MHz

24

220 °C (428 °F)

16.51 mm

24

EPM5128AJI68-15

Altera

UV PLD

Industrial

J Bend

68

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

25 ns

Yes

5.5 V

CMOS

5

Chip Carrier, Window

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

7 Dedicated Inputs, 52 I/O

7

-40 °C (-40 °F)

Quad

S-CQCC-J68

5.08 mm

24.13 mm

No

Labs interconnected by PIA; 8 Labs; 1 External Clock

83.3 MHz

24.13 mm

52

EPM5128AJI68-20

Altera

UV PLD

Industrial

J Bend

68

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

33 ns

Yes

5.5 V

CMOS

5

Chip Carrier, Window

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

7 Dedicated Inputs, 52 I/O

7

-40 °C (-40 °F)

Quad

S-CQCC-J68

5.08 mm

24.13 mm

No

Labs interconnected by PIA; 8 Labs; 1 External Clock

66.7 MHz

24.13 mm

52

EP1210JM-2

Altera

UV PLD

Military

J Bend

44

WQCCJ

Square

Ceramic, Glass-Sealed

65 ns

Yes

5.5 V

CMOS

5

Chip Carrier, Window

Macrocell

4.5 V

1.27 mm

125 °C (257 °F)

12 Dedicated Inputs, 24 I/O

12

-55 °C (-67 °F)

Quad

S-GQCC-J44

4.57 mm

16.51 mm

No

28 Macrocells

23.2 MHz

16.51 mm

24

EPM5130AJC-20

Altera

UV PLD

Commercial

J Bend

84

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

33 ns

Yes

5.25 V

CMOS

5

Chip Carrier, Window

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

19 Dedicated Inputs, 48 I/O

19

0 °C (32 °F)

Quad

S-CQCC-J84

5.08 mm

29.21 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

66.7 MHz

29.21 mm

48

EPS464JC-25

Altera

UV PLD

Commercial

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

25 ns

Yes

5.25 V

CMOS

5

Chip Carrier, Window

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

0 Dedicated Inputs, 32 I/O

0

0 °C (32 °F)

Tin Lead

Quad

S-CQCC-J44

4.826 mm

16.51 mm

No

Macrocells Interconnected By Global Bus; Synchronous Timing Generator; 64 Macrocells

e0

50 MHz

220 °C (428 °F)

16.51 mm

32

EPM5130JM

Altera

UV PLD

Military

J Bend

84

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

55 ns

Yes

5.5 V

128

CMOS

5

5 V

Chip Carrier, Window

LDCC84,1.2SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

125 °C (257 °F)

19 Dedicated Inputs, 48 I/O

19

-55 °C (-67 °F)

Tin Lead

Quad

S-CQCC-J84

5.08 mm

29.21 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

e0

33.3 MHz

220 °C (428 °F)

29.21 mm

No

48

EPM5128AJI68-12

Altera

UV PLD

Industrial

J Bend

68

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

20 ns

Yes

5.5 V

CMOS

5

Chip Carrier, Window

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

7 Dedicated Inputs, 52 I/O

7

-40 °C (-40 °F)

Quad

S-CQCC-J68

5.08 mm

24.13 mm

No

Labs interconnected by PIA; 8 Labs; 1 External Clock

111.1 MHz

24.13 mm

52

EPS448JC-25

Altera

UV PLD

Commercial

J Bend

28

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

Yes

5.25 V

CMOS

5

Chip Carrier, Window

Registered

4.75 V

1.27 mm

70 °C (158 °F)

8 Dedicated Inputs, 0 I/O

8

0 °C (32 °F)

Tin Lead

Quad

S-CQCC-J28

4.826 mm

11.43 mm

No

Stand-Alone Microsequencer

e0

25 MHz

220 °C (428 °F)

11.43 mm

0

EP900JC-1

Altera

UV PLD

Commercial

J Bend

44

WQCCJ

Square

Ceramic, Glass-Sealed

35 ns

Yes

5.25 V

CMOS

36

PAL-TYPE

5

5 V

Chip Carrier, Window

LDCC44,.7SQ

Programmable Logic Devices

Macrocell

4.75 V

240

1.27 mm

70 °C (158 °F)

12 Dedicated Inputs, 24 I/O

12

0 °C (32 °F)

Tin Lead

Quad

S-GQCC-J44

4.57 mm

16.51 mm

No

24 Macrocells

e0

33.3 MHz

24

220 °C (428 °F)

16.51 mm

24

EP910JC44-35

Altera

UV PLD

Commercial

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

38 ns

Yes

5.25 V

CMOS

5

Chip Carrier, Window

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

12 Dedicated Inputs, 24 I/O

12

0 °C (32 °F)

Quad

S-CQCC-J44

4.57 mm

16.51 mm

No

24 Macrocells; 2 External Clocks

28.6 MHz

16.51 mm

24

EP1810JC68-45

Altera

UV PLD

Commercial

J Bend

68

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

50 ns

Yes

5.25 V

CMOS

5

Chip Carrier, Window

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

12 Dedicated Inputs, 48 I/O

12

0 °C (32 °F)

Quad

S-CQCC-J68

5.08 mm

24.13 mm

No

48 Macrocells; Shared Input/Clock

22.2 MHz

24.13 mm

48

EP910JC44-30

Altera

UV PLD

Commercial

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

33 ns

Yes

5.25 V

CMOS

5

Chip Carrier, Window

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

12 Dedicated Inputs, 24 I/O

12

0 °C (32 °F)

Quad

S-CQCC-J44

4.57 mm

16.51 mm

No

24 Macrocells; 2 External Clocks

33.3 MHz

16.51 mm

24

EPM5064JC

Altera

UV PLD

Commercial

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

55 ns

Yes

5.25 V

64

CMOS

5

5 V

Chip Carrier, Window

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

7 Dedicated Inputs, 28 I/O

7

0 °C (32 °F)

Tin Lead

Quad

S-CQCC-J44

4.57 mm

16.51 mm

No

Labs interconnected by PIA; 4 Labs; 64 Macrocells; 1 External Clock; Shared Input/Clock

e0

40 MHz

220 °C (428 °F)

16.51 mm

No

28

EP910JM-40

Altera

UV PLD

Military

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

43 ns

Yes

5.5 V

CMOS

36

PAL-TYPE

5

5 V

Chip Carrier, Window

LDCC44,.7SQ

Programmable Logic Devices

Macrocell

4.5 V

240

1.27 mm

125 °C (257 °F)

12 Dedicated Inputs, 24 I/O

12

-55 °C (-67 °F)

Tin Lead

Quad

S-CQCC-J44

4.826 mm

16.51 mm

No

Macrocells Interconnected By Global Bus; 24 Macrocells; 2 External Clocks

e0

25 MHz

24

220 °C (428 °F)

16.51 mm

24

EPM5032JC-25

Altera

UV PLD

Commercial

J Bend

28

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

25 ns

Yes

5.25 V

CMOS

24

PAL-TYPE

5

5 V

Chip Carrier, Window

LDCC28,.5SQ

Programmable Logic Devices

Macrocell

4.75 V

320

1.27 mm

70 °C (158 °F)

7 Dedicated Inputs, 16 I/O

7

0 °C (32 °F)

Tin Lead

Quad

S-CQCC-J28

4.57 mm

11.43 mm

No

Macrocells interconnected by PIA; 1 LAB; 32 Macrocells; 1 External Clock; Shared Input/Clock

e0

62.5 MHz

16

220 °C (428 °F)

11.43 mm

16

EP600JC-3

Altera

UV PLD

Commercial

J Bend

28

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

45 ns

Yes

5.25 V

CMOS

20

PAL-TYPE

5

5 V

Chip Carrier, Window

LDCC28,.5SQ

Programmable Logic Devices

Macrocell

4.75 V

160

1.27 mm

70 °C (158 °F)

4 Dedicated Inputs, 16 I/O

4

0 °C (32 °F)

Tin Lead

Quad

S-CQCC-J28

4.57 mm

11.43 mm

No

16 Macrocells

e0

26.3 MHz

16

220 °C (428 °F)

11.43 mm

16

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.