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| Manufacturer | Xilinx |
|---|---|
| Manufacturer's Part Number | XC2018-130PC84C |
| Description | FIELD PROGRAMMABLE GATE ARRAY; Grading Of Temperature: OTHER; Form Of Terminal: J BEND; No. of Terminals: 84; Package Code: QCCJ; Package Shape: SQUARE; |
| Datasheet | XC2018-130PC84C Datasheet |
| In Stock | 1,324 |
| NAME | DESCRIPTION |
|---|---|
| Minimum Supply Voltage: | 4.75 V |
| Package Body Material: | Plastic/Epoxy |
| Organization: | 100 CLBS, 1000 Gates |
| Maximum Time At Peak Reflow Temperature (s): | 30 s |
| Maximum Combinatorial Delay of a CLB: | 5.5 ns |
| Maximum Seated Height: | 5.08 mm |
| No. of Inputs: | 74 |
| Sub-Category: | Field Programmable Gate Arrays |
| Surface Mount: | Yes |
| No. of Outputs: | 74 |
| Position Of Terminal: | Quad |
| No. of Terminals: | 84 |
| No. of Equivalent Gates: | 1000 |
| Package Style (Meter): | Chip Carrier |
| JESD-30 Code: | S-PQCC-J84 |
| Maximum Clock Frequency: | 130 MHz |
| Package Shape: | Square |
| Maximum Operating Temperature: | 85 °C (185 °F) |
| Package Code: | QCCJ |
| Width: | 29.3116 mm |
| Moisture Sensitivity Level (MSL): | 3 |
| Grading Of Temperature: | Other |
| Programmable IC Type: | FPGA |
| Maximum Supply Voltage: | 5.25 V |
| Nominal Supply Voltage (V): | 5 |
| Technology Used: | CMOS |
| No. of Logic Cells: | 100 |
| No. of CLBs: | 100 |
| JESD-609 Code: | e0 |
| Minimum Operating Temperature: | 0 °C (32 °F) |
| Qualification: | No |
| Package Equivalence Code: | LDCC84,1.2SQ |
| Finishing Of Terminal Used: | Tin Lead |
| Length: | 29.3116 mm |
| Form Of Terminal: | J Bend |
| Additional Features: | 174 flip-flops; typical gates = 1000-1500 |
| Pitch Of Terminal: | 1.27 mm |
| Peak Reflow Temperature (C): | 225 °C (437 °F) |
| Power Supplies (V): | 5 V |








