Part | RoHS | Manufacturer | Programmable IC Type | Grading Of Temperature | Form Of Terminal | No. of Terminals | Package Code | Package Shape | Total Dose (V) | Package Body Material | No. of Logic Cells | Surface Mount | Maximum Supply Voltage | No. of CLBs | Technology Used | Screening Level | No. of Inputs | No. of Equivalent Gates | Nominal Supply Voltage (V) | Packing Method | Power Supplies (V) | Package Style (Meter) | Package Equivalence Code | Sub-Category | Minimum Supply Voltage | Pitch Of Terminal | Maximum Operating Temperature | Maximum Combinatorial Delay of a CLB | Organization | Minimum Operating Temperature | Finishing Of Terminal Used | Position Of Terminal | JESD-30 Code | Moisture Sensitivity Level (MSL) | Maximum Seated Height | Width | Qualification | Additional Features | JESD-609 Code | Maximum Clock Frequency | Maximum Time At Peak Reflow Temperature (s) | No. of Outputs | Peak Reflow Temperature (C) | Length |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Xilinx |
FPGA |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
3.3 |
Flatpack, Thin Profile, Fine Pitch |
.5 mm |
Quad |
S-PQFP-G100 |
1.2 mm |
14 mm |
No |
14 mm |
||||||||||||||||||||||||||||
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
196 |
Yes |
5.25 V |
196 |
CMOS |
112 |
3000 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.75 V |
.65 mm |
85 °C (185 °F) |
2.7 ns |
196 CLBS, 3000 Gates |
0 °C (32 °F) |
Tin/Lead (Sn85Pb15) |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Max usable 5000 Logic gates |
e0 |
111 MHz |
30 s |
112 |
225 °C (437 °F) |
20 mm |
|||||
Xilinx |
FPGA |
Military |
Flat |
100 |
GQFF |
Square |
Ceramic, Metal-Sealed Cofired |
64 |
Yes |
5.5 V |
CMOS |
MIL-STD-883 |
64 |
2000 |
5 |
5 V |
Flatpack, Guard Ring |
TPAK100,2.6SQ,25 |
Field Programmable Gate Arrays |
4.5 V |
.635 mm |
125 °C (257 °F) |
2000 Gates |
-55 °C (-67 °F) |
Gold |
Quad |
S-CQFP-F100 |
3.2258 mm |
19.05 mm |
No |
e4 |
100 MHz |
64 |
19.05 mm |
||||||||||
Xilinx |
FPGA |
Military |
Flat |
100 |
QFF |
Square |
Yes |
5.5 V |
64 |
CMOS |
MIL-STD-883 |
2000 |
5 |
Flatpack |
4.5 V |
.635 mm |
125 °C (257 °F) |
9 ns |
64 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Gold |
Quad |
S-XQFP-F100 |
3.68 mm |
17.27 mm |
No |
e4 |
25 MHz |
17.27 mm |
|||||||||||||||
|
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
3.6 V |
64 |
CMOS |
2000 |
3.3 |
Flatpack |
3 V |
.65 mm |
85 °C (185 °F) |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Typical gates = 2000-3000 |
e3 |
20 mm |
|||||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
LFQFP |
Square |
Plastic/Epoxy |
Yes |
CMOS |
3.3 |
Flatpack, Low Profile, Fine Pitch |
.5 mm |
Quad |
S-PQFP-G100 |
1.6 mm |
14 mm |
No |
14 mm |
|||||||||||||||||||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
400 |
CMOS |
7000 |
5 |
Flatpack, Thin Profile, Fine Pitch |
4.75 V |
.5 mm |
85 °C (185 °F) |
1.2 ns |
400 CLBS, 7000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
Maximum usable gates 20000 |
e3 |
166 MHz |
30 s |
260 °C (500 °F) |
14 mm |
||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.25 V |
144 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.65 mm |
85 °C (185 °F) |
4.1 ns |
144 CLBS, 2000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
Max usable 3000 Logic gates |
e3 |
135 MHz |
30 s |
245 °C (473 °F) |
20 mm |
|||||||||||
|
Xilinx |
FPGA |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
196 |
CMOS |
6000 |
5 |
Flatpack, Thin Profile, Fine Pitch |
4.5 V |
.5 mm |
3.8 ns |
196 CLBS, 6000 Gates |
Matte Tin |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
Typical gates = 6000-10000 |
e3 |
83 MHz |
30 s |
260 °C (500 °F) |
14 mm |
|||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
LFQFP |
Square |
Plastic/Epoxy |
Yes |
CMOS |
3.3 |
Flatpack, Low Profile, Fine Pitch |
.5 mm |
Quad |
S-PQFP-G100 |
1.6 mm |
14 mm |
No |
14 mm |
|||||||||||||||||||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
144 |
CMOS |
2000 |
5 |
Flatpack, Thin Profile, Fine Pitch |
4.75 V |
.5 mm |
85 °C (185 °F) |
5.1 ns |
144 CLBS, 2000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
Max usable 3000 Logic gates |
e3 |
113 MHz |
30 s |
260 °C (500 °F) |
14 mm |
|||||||||||
Xilinx |
FPGA |
Military |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.5 V |
144 |
CMOS |
MIL-PRF-38535 Class Q |
4200 |
5 |
Flatpack |
4.5 V |
125 °C (257 °F) |
14 ns |
144 CLBS, 4200 Gates |
-55 °C (-67 °F) |
Quad |
S-CQFP-F100 |
50 MHz |
|||||||||||||||||||||
Xilinx |
FPGA |
Military |
Flat |
100 |
GQFF |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
Yes |
CMOS |
MIL-STD-883 |
82 |
5 |
5 V |
Flatpack, Guard Ring |
TPAK100,2.6SQ,25 |
Field Programmable Gate Arrays |
.65 mm |
125 °C (257 °F) |
9 ns |
-55 °C (-67 °F) |
Gold |
Quad |
S-CQFP-F100 |
3.429 mm |
19.05 mm |
No |
e4 |
70 MHz |
82 |
19.05 mm |
|||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
CMOS |
5 |
Flatpack |
.65 mm |
Quad |
R-PQFP-G100 |
3.4 mm |
14 mm |
No |
20 mm |
|||||||||||||||||||||||||||
|
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.5 V |
196 |
CMOS |
3000 |
5 |
Flatpack |
4.5 V |
.65 mm |
2.7 ns |
196 CLBS, 3000 Gates |
Matte Tin |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Max usable 5000 Logic gates |
e3 |
111 MHz |
30 s |
245 °C (473 °F) |
20 mm |
|||||||||||||
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
64 |
Yes |
5.25 V |
64 |
CMOS |
64 |
1000 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.75 V |
.65 mm |
85 °C (185 °F) |
7 ns |
64 CLBS, 1000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
R-PQFP-G100 |
3 |
2.87 mm |
14 mm |
No |
256 flip-flops; typical gates = 1000-1500; power-down supplier current = 50 µA |
e0 |
100 MHz |
30 s |
64 |
225 °C (437 °F) |
20 mm |
|||||
Xilinx |
FPGA |
Industrial |
Gull Wing |
100 |
QFP |
Square |
Plastic/Epoxy |
144 |
Yes |
CMOS |
82 |
5 |
5 V |
Flatpack |
QFP100,.63SQ,20 |
Field Programmable Gate Arrays |
.5 mm |
85 °C (185 °F) |
-40 °C (-40 °F) |
Tin Lead |
Quad |
S-PQFP-G100 |
3 |
No |
e0 |
30 s |
82 |
225 °C (437 °F) |
||||||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
64 |
Yes |
3.6 V |
64 |
CMOS |
64 |
1000 |
3.3 |
3.3 V |
Flatpack, Thin Profile, Fine Pitch |
TQFP100,.63SQ |
Field Programmable Gate Arrays |
3 V |
.5 mm |
1.3 ns |
64 CLBS, 1000 Gates |
Tin Lead |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
Max usable 1600 Logic gates |
e0 |
200 MHz |
30 s |
64 |
240 °C (464 °F) |
14 mm |
||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
3.6 V |
64 |
CMOS |
1000 |
3.3 |
Flatpack, Thin Profile, Fine Pitch |
3 V |
.5 mm |
85 °C (185 °F) |
1.2 ns |
64 CLBS, 1000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
Max usable 1600 Logic gates |
e3 |
217 MHz |
30 s |
260 °C (500 °F) |
14 mm |
||||||||||
|
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.5 V |
120 |
CMOS |
4000 |
5 |
Flatpack |
4.5 V |
.65 mm |
3 ns |
120 CLBS, 4000 Gates |
Matte Tin |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Typical gates = 4000-6000 |
e3 |
83 MHz |
30 s |
245 °C (473 °F) |
20 mm |
|||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.25 V |
1024 |
CMOS |
3000 |
5 |
Flatpack |
4.75 V |
.65 mm |
70 °C (158 °F) |
1024 CLBS, 3000 Gates |
0 °C (32 °F) |
Quad |
R-PQFP-G100 |
3.4 mm |
14 mm |
No |
512 flip-flops; 3.3 V operation; OTP based |
20 mm |
||||||||||||||||||
Xilinx |
FPGA |
Industrial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.5 V |
1024 |
CMOS |
3328 |
5 |
Flatpack |
4.5 V |
.65 mm |
85 °C (185 °F) |
5.5 ns |
1024 CLBS, 3328 Gates |
-40 °C (-40 °F) |
Quad |
R-PQFP-G100 |
3.4 mm |
14 mm |
No |
MAX 64 I/OS; MAX 512 flip-flops; OTP based |
20 mm |
|||||||||||||||||
|
Xilinx |
FPGA |
Industrial |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
2160 |
Yes |
1.26 V |
240 |
CMOS |
66 |
100000 |
1.2 |
1.2,1.2/3.3,2.5 V |
Flatpack, Thin Profile, Fine Pitch |
TQFP100,.63SQ |
Field Programmable Gate Arrays |
1.14 V |
.5 mm |
100 °C (212 °F) |
0.76 ns |
240 CLBS, 100000 Gates |
-40 °C (-40 °F) |
Nickel Palladium Gold |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
e4 |
572 MHz |
59 |
14 mm |
|||||||
|
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.5 V |
100 |
CMOS |
2000 |
5 |
Flatpack |
4.5 V |
.65 mm |
2 ns |
100 CLBS, 2000 Gates |
Matte Tin |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Max usable 3000 Logic gates |
e3 |
125 MHz |
30 s |
245 °C (473 °F) |
20 mm |
|||||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
100 |
CMOS |
2000 |
5 |
Flatpack, Thin Profile, Fine Pitch |
4.75 V |
.5 mm |
85 °C (185 °F) |
1.3 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
Max usable 3000 Logic gates |
e3 |
166 MHz |
30 s |
260 °C (500 °F) |
14 mm |
||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.25 V |
120 |
CMOS |
4000 |
5 |
Flatpack |
4.75 V |
.65 mm |
85 °C (185 °F) |
4.6 ns |
120 CLBS, 4000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
MAX available 6000 Logic gates |
e3 |
83 MHz |
30 s |
245 °C (473 °F) |
20 mm |
||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
576 |
Yes |
3.6 V |
576 |
CMOS |
196 |
10000 |
3.3 |
3.3 V |
Flatpack, Thin Profile, Fine Pitch |
TQFP100,.63SQ |
Field Programmable Gate Arrays |
3 V |
.5 mm |
85 °C (185 °F) |
1.1 ns |
576 CLBS, 10000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
Maximum usable gates 30000 |
e3 |
217 MHz |
30 s |
196 |
260 °C (500 °F) |
14 mm |
||||
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
LFQFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
100 |
CMOS |
1500 |
5 |
Flatpack, Low Profile, Fine Pitch |
4.75 V |
.5 mm |
85 °C (185 °F) |
7 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Quad |
S-PQFP-G100 |
1.7 mm |
14 mm |
No |
360 flip-flops; typical gates = 1500-2000 |
100 MHz |
14 mm |
||||||||||||||||
Xilinx |
FPGA |
Industrial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
64 |
1000 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.5 V |
.65 mm |
85 °C (185 °F) |
5.1 ns |
64 CLBS, 1000 Gates |
-40 °C (-40 °F) |
Tin/Lead (Sn85Pb15) |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Max usable 1500 Logic gates |
e0 |
113 MHz |
30 s |
64 |
225 °C (437 °F) |
20 mm |
|||||
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
3.6 V |
196 |
3000 |
3.3 |
Flatpack |
3 V |
.65 mm |
1.2 ns |
196 CLBS, 3000 Gates |
Matte Tin |
Quad |
R-PQFP-G100 |
3.4 mm |
14 mm |
No |
Can also use 9000 gates |
e3 |
217 MHz |
20 mm |
||||||||||||||||||
Xilinx |
FPGA |
Industrial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.5 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.5 V |
.635 mm |
85 °C (185 °F) |
9 ns |
64 CLBS, 2000 Gates |
-40 °C (-40 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
70 MHz |
17.272 mm |
||||||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.65 mm |
85 °C (185 °F) |
4.6 ns |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
MAX available 3000 Logic gates |
e3 |
83 MHz |
30 s |
245 °C (473 °F) |
20 mm |
||||||||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.635 mm |
70 °C (158 °F) |
7 ns |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
100 MHz |
17.272 mm |
||||||||||||||
Xilinx |
FPGA |
Industrial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
144 |
Yes |
5.5 V |
144 |
CMOS |
82 |
2000 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.5 V |
.65 mm |
85 °C (185 °F) |
7 ns |
144 CLBS, 2000 Gates |
-40 °C (-40 °F) |
Tin Lead |
Quad |
R-PQFP-G100 |
3 |
2.87 mm |
14 mm |
No |
480 flip-flops; typical gates = 2000-3000; power-down supplier current = 120 µA |
e0 |
100 MHz |
30 s |
82 |
225 °C (437 °F) |
20 mm |
|||||
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
80 |
1500 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.75 V |
.65 mm |
85 °C (185 °F) |
9 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
R-PQFP-G100 |
3 |
2.87 mm |
14 mm |
No |
360 flip-flops; typical gates = 1500-2000; power-down supplier current = 80 µA |
e0 |
70 MHz |
30 s |
80 |
225 °C (437 °F) |
20 mm |
|||||
Xilinx |
FPGA |
Military |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
64 |
Yes |
5.5 V |
64 |
CMOS |
38535Q/M;38534H;883B |
64 |
2000 |
5 |
5 V |
Flatpack |
QFL100,.7SQ,25 |
Field Programmable Gate Arrays |
4.5 V |
.635 mm |
125 °C (257 °F) |
9 ns |
64 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
1 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops |
e0 |
70 MHz |
64 |
17.272 mm |
||||||
Xilinx |
FPGA |
Military |
Flat |
100 |
GQFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
144 |
CMOS |
2000 |
5 |
Flatpack, Guard Ring |
.65 mm |
125 °C (257 °F) |
9 ns |
144 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Quad |
S-CQFP-F100 |
2.921 mm |
19.05 mm |
No |
480 flip-flops; typical gates = 2000-3000 |
70 MHz |
19.05 mm |
||||||||||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
1.26 V |
192 |
50000 |
1.2 |
Flatpack, Thin Profile, Fine Pitch |
1.14 V |
.5 mm |
85 °C (185 °F) |
192 CLBS, 50000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
e3 |
30 s |
260 °C (500 °F) |
14 mm |
||||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
LFQFP |
Square |
Plastic/Epoxy |
Yes |
CMOS |
3.3 |
Flatpack, Low Profile, Fine Pitch |
.5 mm |
Quad |
S-PQFP-G100 |
1.6 mm |
14 mm |
No |
70 MHz |
14 mm |
||||||||||||||||||||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
3.6 V |
196 |
CMOS |
3000 |
3.3 |
Flatpack |
3 V |
.65 mm |
85 °C (185 °F) |
1.2 ns |
196 CLBS, 3000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Max usable 5000 Logic gates |
e3 |
217 MHz |
20 mm |
||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
84 |
2000 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.5 V |
.65 mm |
3.8 ns |
64 CLBS, 2000 Gates |
Tin/Lead (Sn85Pb15) |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Typical gates = 2000-3000 |
e0 |
83 MHz |
30 s |
84 |
225 °C (437 °F) |
20 mm |
||||||||
Xilinx |
FPGA |
Military |
Flat |
100 |
GQFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
144 |
CMOS |
2000 |
5 |
Flatpack, Guard Ring |
.65 mm |
125 °C (257 °F) |
7 ns |
144 CLBS, 2000 Gates |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
2.921 mm |
19.05 mm |
No |
480 flip-flops; typical gates = 2000-3000 |
e0 |
100 MHz |
19.05 mm |
||||||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
64 |
1000 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.5 V |
.65 mm |
2.7 ns |
64 CLBS, 1000 Gates |
Tin Lead |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Max usable 1500 Logic gates |
e0 |
270 MHz |
30 s |
64 |
225 °C (437 °F) |
20 mm |
||||||||
|
Xilinx |
FPGA |
Other |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
196 |
CMOS |
6000 |
5 |
Flatpack, Thin Profile, Fine Pitch |
4.75 V |
.5 mm |
85 °C (185 °F) |
5.6 ns |
196 CLBS, 6000 Gates |
0 °C (32 °F) |
Matte Tin |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
MAX available 10000 Logic gates |
e3 |
83 MHz |
30 s |
260 °C (500 °F) |
14 mm |
||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
3.6 V |
64 |
CMOS |
2000 |
3.3 |
Flatpack |
3 V |
.65 mm |
85 °C (185 °F) |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
Typical gates = 2000-3000 |
e0 |
20 mm |
||||||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
Yes |
1.26 V |
192 |
50000 |
1.2 |
Flatpack, Thin Profile, Fine Pitch |
1.14 V |
.5 mm |
192 CLBS, 50000 Gates |
Tin Lead |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
e0 |
14 mm |
||||||||||||||||||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.635 mm |
70 °C (158 °F) |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
50 MHz |
17.272 mm |
|||||||||||||||
Xilinx |
FPGA |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
CMOS |
5 |
Flatpack |
.65 mm |
Quad |
R-PQFP-G100 |
3.4 mm |
14 mm |
No |
20 mm |
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits that are programmable by the user to perform specific logic functions. They consist of a matrix of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes FPGAs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.
FPGAs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the FPGA hardware. The resulting configuration data is then loaded onto the FPGA, allowing it to perform the desired logic functions.
FPGAs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.