Part | RoHS | Manufacturer | Programmable IC Type | Grading Of Temperature | Form Of Terminal | No. of Terminals | Package Code | Package Shape | Total Dose (V) | Package Body Material | No. of Logic Cells | Surface Mount | Maximum Supply Voltage | No. of CLBs | Technology Used | Screening Level | No. of Inputs | No. of Equivalent Gates | Nominal Supply Voltage (V) | Packing Method | Power Supplies (V) | Package Style (Meter) | Package Equivalence Code | Sub-Category | Minimum Supply Voltage | Pitch Of Terminal | Maximum Operating Temperature | Maximum Combinatorial Delay of a CLB | Organization | Minimum Operating Temperature | Finishing Of Terminal Used | Position Of Terminal | JESD-30 Code | Moisture Sensitivity Level (MSL) | Maximum Seated Height | Width | Qualification | Additional Features | JESD-609 Code | Maximum Clock Frequency | Maximum Time At Peak Reflow Temperature (s) | No. of Outputs | Peak Reflow Temperature (C) | Length |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
100 |
CMOS |
1500 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
85 °C (185 °F) |
7 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
4.445 mm |
24.2316 mm |
No |
360 flip-flops; typical gates = 1500-2000 |
100 MHz |
24.2316 mm |
||||||||||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
CMOS |
3.3 |
Chip Carrier |
1.27 mm |
Quad |
S-PQCC-J68 |
5.08 mm |
24.2316 mm |
No |
24.2316 mm |
|||||||||||||||||||||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
100 |
CMOS |
1500 |
5 |
Chip Carrier |
4.5 V |
1.27 mm |
7 ns |
100 CLBS, 1500 Gates |
Quad |
S-PQCC-J68 |
4.445 mm |
24.2316 mm |
No |
360 flip-flops; typical gates = 1500-2000 |
100 MHz |
24.2316 mm |
|||||||||||||||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
58 |
1500 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
3.3 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
3 |
5.08 mm |
24.2316 mm |
No |
Max usable 2000 Logic gates |
e0 |
227 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
85 °C (185 °F) |
7 ns |
64 CLBS, 1000 Gates |
-40 °C (-40 °F) |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
256 flip-flops; typical gates = 1000-1500; power-down supplier current = 50 µA |
100 MHz |
58 |
24.2316 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
CMOS |
58 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
No |
e0 |
325 MHz |
58 |
||||||||||||||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.5 V |
100 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
85 °C (185 °F) |
10 ns |
100 CLBS, 1000 Gates |
-40 °C (-40 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
174 flip-flops; typical gates = 1000-1500 |
e0 |
70 MHz |
58 |
24.2316 mm |
|||||||
|
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
100 |
CMOS |
1500 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
85 °C (185 °F) |
4.1 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
5.08 mm |
24.2316 mm |
Max usable 2000 Logic gates |
135 MHz |
24.2316 mm |
||||||||||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
2.2 ns |
64 CLBS, 1000 Gates |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Max usable 1500 Logic gates |
e0 |
323 MHz |
58 |
24.2316 mm |
||||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
CMOS |
5 |
Chip Carrier |
1.27 mm |
Quad |
S-PQCC-J68 |
5.08 mm |
24.2316 mm |
No |
70 MHz |
24.2316 mm |
||||||||||||||||||||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
3.3 ns |
64 CLBS, 1000 Gates |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Max usable 1500 Logic gates |
e0 |
227 MHz |
58 |
24.2316 mm |
||||||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
3.6 V |
64 |
CMOS |
1000 |
3.3 |
Chip Carrier |
3 V |
1.27 mm |
85 °C (185 °F) |
64 CLBS, 1000 Gates |
-40 °C (-40 °F) |
Quad |
S-PQCC-J68 |
4.445 mm |
24.2316 mm |
No |
MAX 58 I/OS; 800 to 1000 available gates |
24.2316 mm |
||||||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.25 V |
64 |
CMOS |
58 |
600 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
15 ns |
64 CLBS, 600 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
MAX 58 I/OS; 122 flip-flops; typical gates = 600 - 1000 |
e0 |
50 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
144 |
Yes |
CMOS |
58 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
No |
100 MHz |
58 |
||||||||||||||||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.25 V |
64 |
CMOS |
58 |
600 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
7.5 ns |
64 CLBS, 600 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
122 flip-flops; typical gates = 600-1000 |
e0 |
100 MHz |
58 |
24.2316 mm |
|||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
68 |
PGA |
Square |
Ceramic |
64 |
No |
CMOS |
38535Q/M;38534H;883B |
58 |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Field Programmable Gate Arrays |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Perpendicular |
S-XPGA-P68 |
No |
33 MHz |
58 |
||||||||||||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
CMOS |
5 |
Chip Carrier |
1.27 mm |
Quad |
S-PQCC-J68 |
5.08 mm |
24.2316 mm |
No |
24.2316 mm |
|||||||||||||||||||||||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.25 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
1.5 ns |
64 CLBS, 1000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Max usable 1500 Logic gates |
e0 |
370 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
85 °C (185 °F) |
5.1 ns |
64 CLBS, 1000 Gates |
-40 °C (-40 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
3 |
5.08 mm |
24.2316 mm |
No |
Max usable 1500 Logic gates |
e0 |
113 MHz |
58 |
24.2316 mm |
|||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
68 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
64 |
No |
5.5 V |
64 |
CMOS |
58 |
600 |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
125 °C (257 °F) |
15 ns |
64 CLBS, 600 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P68 |
4.064 mm |
27.94 mm |
No |
122 flip-flops; typical gates = 600-1000 |
50 MHz |
58 |
27.94 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
100 |
CMOS |
3000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
7 ns |
100 CLBS, 3000 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
4.699 mm |
24.2316 mm |
No |
MAX 58 I/OS; 360 flip-flops; power-down supplier current = 2 µA @ VCC = 3.2 V & T = 25°C |
100 MHz |
24.2316 mm |
||||||||||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
68 |
PGA |
Square |
Ceramic |
64 |
No |
CMOS |
58 |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Field Programmable Gate Arrays |
2.54 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Perpendicular |
S-XPGA-P68 |
No |
33 MHz |
58 |
|||||||||||||||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
58 |
1500 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
2.2 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Max usable 2000 Logic gates |
e0 |
323 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
64 |
CMOS |
1000 |
5 |
Chip Carrier |
4.5 V |
1.27 mm |
7 ns |
64 CLBS, 1000 Gates |
Quad |
S-PQCC-J68 |
4.445 mm |
24.2316 mm |
No |
256 flip-flops; typical gates = 1000-1500 |
100 MHz |
24.2316 mm |
|||||||||||||||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
58 |
1500 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
9 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
360 flip-flops; typical gates = 1500-2000; power-down supplier current = 80 µA |
e0 |
70 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
CMOS |
5 |
Chip Carrier |
1.27 mm |
Quad |
S-PQCC-J68 |
5.08 mm |
24.2316 mm |
No |
24.2316 mm |
|||||||||||||||||||||||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.5 V |
100 |
CMOS |
58 |
1500 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
85 °C (185 °F) |
9 ns |
100 CLBS, 1500 Gates |
-40 °C (-40 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
360 flip-flops; typical gates = 1500-2000; power-down supplier current = 80 µA |
e0 |
70 MHz |
58 |
24.2316 mm |
|||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
68 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
64 |
No |
5.25 V |
64 |
CMOS |
58 |
600 |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
5.5 ns |
64 CLBS, 600 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P68 |
4.064 mm |
27.94 mm |
No |
122 flip-flops; typical gates = 600-1000 |
130 MHz |
58 |
27.94 mm |
|||||||||
|
Xilinx |
FPGA |
Other |
Pin/Peg |
68 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
64 |
No |
5.25 V |
64 |
CMOS |
58 |
600 |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
85 °C (185 °F) |
7.5 ns |
64 CLBS, 600 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P68 |
4.064 mm |
27.94 mm |
No |
122 flip-flops; typical gates = 600-1000 |
100 MHz |
58 |
27.94 mm |
|||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
64 |
CMOS |
1000 |
5 |
Chip Carrier |
4.5 V |
1.27 mm |
9 ns |
64 CLBS, 1000 Gates |
Tin Lead |
Quad |
S-PQCC-J68 |
4.445 mm |
24.2316 mm |
No |
256 flip-flops; typical gates = 1000-1500 |
e0 |
70 MHz |
24.2316 mm |
|||||||||||||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
85 °C (185 °F) |
3.3 ns |
64 CLBS, 1000 Gates |
-40 °C (-40 °F) |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Typical gates = 1000-1500 |
227 MHz |
58 |
24.2316 mm |
|||||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
64 |
CMOS |
2000 |
5 |
Chip Carrier |
4.5 V |
1.27 mm |
85 °C (185 °F) |
64 CLBS, 2000 Gates |
-40 °C (-40 °F) |
Quad |
S-PQCC-J68 |
4.699 mm |
24.2316 mm |
No |
MAX 58 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
50 MHz |
24.2316 mm |
|||||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
CMOS |
58 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
No |
70 MHz |
58 |
||||||||||||||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
64 |
CMOS |
1000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
1.8 ns |
64 CLBS, 1000 Gates |
Quad |
S-PQCC-J68 |
5.08 mm |
24.2316 mm |
No |
Typical gates = 1000-1500 |
323 MHz |
24.2316 mm |
|||||||||||||||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
85 °C (185 °F) |
4.1 ns |
64 CLBS, 1000 Gates |
-40 °C (-40 °F) |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Typical gates = 1000-1500 |
188 MHz |
58 |
24.2316 mm |
|||||||||
|
Xilinx |
FPGA |
Military |
Pin/Peg |
68 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
64 |
No |
5.5 V |
64 |
CMOS |
58 |
600 |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Field Programmable Gate Arrays |
4.5 V |
2.54 mm |
125 °C (257 °F) |
10 ns |
64 CLBS, 600 Gates |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P68 |
4.064 mm |
27.94 mm |
No |
122 flip-flops; typical gates = 600-1000 |
70 MHz |
58 |
27.94 mm |
|||||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
58 |
1500 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
1.75 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Max usable 2000 Logic gates |
e0 |
323 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
9 ns |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
4.699 mm |
24.2316 mm |
No |
MAX 58 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
70 MHz |
24.2316 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
100 |
CMOS |
3000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
100 CLBS, 3000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
4.699 mm |
24.2316 mm |
No |
MAX 58 I/OS; 360 flip-flops; power-down supplier current = 2 µA @ VCC = 3.2 V & T = 25°C |
e0 |
50 MHz |
24.2316 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.25 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
4.1 ns |
64 CLBS, 1000 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Typical gates = 1000-1500 |
188 MHz |
58 |
24.2316 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
CMOS |
58 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
No |
33 MHz |
58 |
||||||||||||||||||||
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
2.7 ns |
64 CLBS, 1000 Gates |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Max usable 1500 Logic gates |
e0 |
270 MHz |
58 |
24.2316 mm |
||||||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.25 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
7 ns |
64 CLBS, 1000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
256 flip-flops; typical gates = 1000-1500; power-down supplier current = 50 µA |
e0 |
100 MHz |
58 |
24.2316 mm |
|||||||
|
Xilinx |
FPGA |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
64 |
CMOS |
1000 |
5 |
Chip Carrier |
4.5 V |
1.27 mm |
5.1 ns |
64 CLBS, 1000 Gates |
Quad |
S-PQCC-J68 |
5.08 mm |
24.2316 mm |
Max usable 1500 Logic gates |
113 MHz |
24.2316 mm |
|||||||||||||||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
58 |
1500 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
4.1 ns |
100 CLBS, 1500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
5.08 mm |
24.2316 mm |
No |
Typical gates = 1500-2000 |
e0 |
188 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
Other |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.25 V |
64 |
CMOS |
58 |
1000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
85 °C (185 °F) |
4.1 ns |
64 CLBS, 1000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
3 |
5.08 mm |
24.2316 mm |
No |
Max usable 1500 Logic gates |
e0 |
135 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
5.5 V |
64 |
CMOS |
58 |
600 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
85 °C (185 °F) |
8 ns |
64 CLBS, 600 Gates |
-40 °C (-40 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
122 flip-flops; typical gates = 600-1000 |
e0 |
100 MHz |
58 |
24.2316 mm |
|||||||
Xilinx |
FPGA |
Industrial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.5 V |
100 |
CMOS |
58 |
3000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.5 V |
1.27 mm |
85 °C (185 °F) |
100 CLBS, 3000 Gates |
-40 °C (-40 °F) |
Quad |
S-PQCC-J68 |
1 |
4.699 mm |
24.2316 mm |
No |
MAX 58 I/OS; 360 flip-flops |
50 MHz |
58 |
24.2316 mm |
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits that are programmable by the user to perform specific logic functions. They consist of a matrix of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes FPGAs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.
FPGAs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the FPGA hardware. The resulting configuration data is then loaded onto the FPGA, allowing it to perform the desired logic functions.
FPGAs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.