Pin/Peg Programmable Logic Devices (PLD) 482

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Part RoHS Manufacturer Programmable IC Type Grading Of Temperature Form Of Terminal No. of Terminals Package Code Package Shape Package Body Material Propagation Delay No. of Logic Cells Surface Mount Maximum Supply Voltage No. of Macro Cells Technology Used Screening Level No. of Inputs Architecture Nominal Supply Voltage (V) Packing Method Power Supplies (V) Package Style (Meter) Package Equivalence Code Sub-Category In-System Programmable Output Function Minimum Supply Voltage No. of Product Terms Pitch Of Terminal Maximum Operating Temperature Organization No. of Dedicated Inputs Minimum Operating Temperature Finishing Of Terminal Used Position Of Terminal JESD-30 Code Moisture Sensitivity Level (MSL) Maximum Seated Height Width Qualification Additional Features JESD-609 Code Maximum Clock Frequency Maximum Time At Peak Reflow Temperature (s) No. of Outputs Peak Reflow Temperature (C) Length JTAG Boundary Scan Test No. of I/O Lines

EPM9560GC280-12

Altera

EE PLD

Commercial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

13.4 ns

No

5.25 V

CMOS

5

Grid Array

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 216 I/O

0

0 °C (32 °F)

Perpendicular

S-CPGA-P280

5.081 mm

49.78 mm

No

772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V

125 MHz

49.78 mm

216

EPF10K130VGC599-4

Altera

Loadable PLD

Commercial

Pin/Peg

599

IPGA

Square

Ceramic, Metal-Sealed Cofired

0.9 ns

832

No

3.6 V

CMOS

470

3.3

3.3 V

Grid Array, Interstitial Pitch

SPGA599,47X47

Field Programmable Gate Arrays

Registered

3 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 470 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P599

1

5.08 mm

62.484 mm

No

e0

466

220 °C (428 °F)

62.484 mm

470

EPF81188AGM232-2

Altera

Loadable PLD

Military

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.5 V

CMOS

5

Grid Array

Registered

4.5 V

2.54 mm

125 °C (257 °F)

4 Dedicated Inputs, 180 I/O

4

-55 °C (-67 °F)

Perpendicular

S-CPGA-P232

5.207 mm

44.7 mm

No

1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V

44.7 mm

180

EPM9320GI280-15

Altera

EE PLD

Industrial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

16 ns

No

5.5 V

320

CMOS

5

3.3/5,5 V

Grid Array

PGA280,19X19

Programmable Logic Devices

Yes

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

0 Dedicated Inputs, 168 I/O

0

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P280

1

5.08 mm

49.78 mm

No

320 Macrocells

e0

117.6 MHz

220 °C (428 °F)

49.78 mm

Yes

168

EPF8636AGC192-A-4

Altera

Loadable PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

1.9 ns

No

3.6 V

CMOS

3.3

Grid Array

Registered

3 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 136 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

Can also operate at 5 V supply

45.15 mm

136

5962-9314401MYX

Altera

UV PLD

Military

Pin/Peg

100

PGA

Square

Ceramic, Metal-Sealed Cofired

75 ns

No

5.5 V

CMOS

MIL-STD-883 Class B

5

Grid Array

Macrocell

4.5 V

125 °C (257 °F)

19 Dedicated Inputs, 64 I/O

19

-55 °C (-67 °F)

Perpendicular

S-CPGA-P100

No

22.2 MHz

64

EPM7192GC160-15

Altera

EE PLD

Commercial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.25 V

192

CMOS

5

5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 120 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P160

1

5.34 mm

39.624 mm

No

192 Macrocells; Shared Input/Clock

e0

76.9 MHz

220 °C (428 °F)

39.624 mm

No

120

EPM5192GI84

Altera

UV PLD

Industrial

Pin/Peg

84

WPGA

Square

Ceramic, Metal-Sealed Cofired

55 ns

No

5.5 V

192

CMOS

5

5 V

Grid Array, Window

PGA84M,11X11

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

7 Dedicated Inputs, 64 I/O

7

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P84

1

4.96 mm

28.448 mm

No

192 Macrocells; Shared Input/Clock; Shared Product Terms

e0

33.3 MHz

220 °C (428 °F)

28.448 mm

No

64

5962-8946901YX

Altera

UV PLD

Military

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

55 ns

No

5.5 V

48

CMOS

38535Q/M;38534H;883B

5

5 V

Grid Array, Window

PGA68,11X11

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

12 Dedicated Inputs, 48 I/O

12

-55 °C (-67 °F)

Gold

Perpendicular

S-CPGA-P68

3.81 mm

27.94 mm

No

Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks

e4

22.2 MHz

220 °C (428 °F)

27.94 mm

No

48

EPF81188AGC232-2H

Altera

Loadable PLD

Commercial

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.25 V

CMOS

5

Grid Array

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 184 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P232

5.207 mm

No

44.7 mm

184

EPM7192EGC160-15

Altera

EE PLD

Commercial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.25 V

192

CMOS

5

3.3/5,5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 124 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P160

1

5.34 mm

39.624 mm

No

Configurable I/O operation with 3.3 V or 5 V

e0

100 MHz

220 °C (428 °F)

39.624 mm

No

124

EPF8452GI160-3

Altera

Loadable PLD

Industrial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.5 V

CMOS

5

Grid Array

Registered

4.5 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 116 I/O

4

-40 °C (-40 °F)

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

Labs With Fasttrack Interconnect; 452 Flip Flops; 336 Logic Elements

39.624 mm

116

EPF8820AGC192-3

Altera

Loadable PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

672

No

5.25 V

CMOS

152

5

3.3/5,5 V

Grid Array

PGA192M,17X17

Field Programmable Gate Arrays

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 152 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P192

1

5.43 mm

45.15 mm

No

672 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

385 MHz

148

220 °C (428 °F)

45.15 mm

152

EPM5128AGM68-20

Altera

UV PLD

Military

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

33 ns

No

5.5 V

CMOS

5

Grid Array, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

7 Dedicated Inputs, 52 I/O

7

-55 °C (-67 °F)

Perpendicular

S-CPGA-P68

4.953 mm

27.94 mm

No

Labs interconnected by PIA; 8 Labs; 1 External Clock

66.7 MHz

27.94 mm

52

EPM5128AG5962-20

Altera

UV PLD

Military

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

33 ns

No

5.5 V

CMOS

5

Grid Array, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

7 Dedicated Inputs, 52 I/O

7

-55 °C (-67 °F)

Perpendicular

S-CPGA-P68

3.81 mm

27.94 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

66.7 MHz

27.94 mm

52

EPM7192GI160-20

Altera

EE PLD

Industrial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

20 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

0 Dedicated Inputs, 120 I/O

0

-40 °C (-40 °F)

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

192 Macrocells; Shared Input/Clock

62.5 MHz

39.624 mm

120

EPF8820AGC192-2A

Altera

Loadable PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.25 V

CMOS

5

Grid Array

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 152 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P192

1

5.43 mm

45.15 mm

No

220 °C (428 °F)

45.15 mm

152

EPM9320GC280-12

Altera

EE PLD

Commercial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

12.8 ns

No

5.25 V

320

CMOS

5

3.3/5,5 V

Grid Array

PGA280,19X19

Programmable Logic Devices

Yes

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 168 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P280

1

5.081 mm

49.78 mm

No

484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V

e0

125 MHz

220 °C (428 °F)

49.78 mm

Yes

168

EPF8452AGI160-3

Altera

Loadable PLD

Industrial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

336

No

5.5 V

CMOS

120

5

3.3/5,5 V

Grid Array

PGA160M,15X15

Field Programmable Gate Arrays

Registered

4.5 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 120 I/O

4

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P160

1

5.34 mm

39.624 mm

No

336 Logic Elements

e0

385 MHz

116

220 °C (428 °F)

39.624 mm

120

EPM5130GC100-2

Altera

UV PLD

Commercial

Pin/Peg

100

WPGA

Square

Ceramic, Metal-Sealed Cofired

45 ns

No

5.25 V

CMOS

5

Grid Array, Window

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

19 Dedicated Inputs, 64 I/O

19

0 °C (32 °F)

Perpendicular

S-CPGA-P100

4.96 mm

33.528 mm

No

128 Macrocells; Shared Input/Clock; Shared Product Terms

40 MHz

33.528 mm

64

EPF8452AGI160-5

Altera

Loadable PLD

Industrial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.5 V

CMOS

5

Grid Array

Registered

4.5 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 116 I/O

4

-40 °C (-40 °F)

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

452 Flip Flops; 336 Logic Elements

39.624 mm

116

5962-8854901YC

Altera

UV PLD

Military

Pin/Peg

68

PGA

Square

85 ns

No

5.5 V

CMOS

MIL-STD-883

5

Grid Array

Macrocell

4.5 V

125 °C (257 °F)

11 Dedicated Inputs, 48 I/O

11

-55 °C (-67 °F)

Perpendicular

S-XPGA-P68

No

12.2 MHz

48

EPM7256EG5962192-15

Altera

EE PLD

Military

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 160 I/O

0

-55 °C (-67 °F)

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

76.9 MHz

45.15 mm

160

EPM7256EGC192-12P

Altera

EE PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

12 ns

No

5.25 V

256

CMOS

5

3.3/5,5 V

Grid Array

PGA192M,17X17

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 160 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P192

1

5.43 mm

45.15 mm

No

Configurable I/O operation with 3.3 V or 5 V

e0

90.9 MHz

220 °C (428 °F)

45.15 mm

No

160

EP1810GI-25

Altera

UV PLD

Industrial

Pin/Peg

68

PGA

Square

Ceramic, Metal-Sealed Cofired

28 ns

No

5.5 V

48

CMOS

5

5 V

Grid Array

PGA68,11X11

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

12 Dedicated Inputs, 48 I/O

12

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P68

1

No

Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks

e0

40 MHz

220 °C (428 °F)

No

48

EPM5130GC

Altera

UV PLD

Commercial

Pin/Peg

100

PGA

Square

Ceramic, Metal-Sealed Cofired

55 ns

No

5.25 V

128

CMOS

5

5 V

Grid Array

PGA100M,13X13

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

19 Dedicated Inputs, 64 I/O

19

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P100

1

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

e0

33.3 MHz

220 °C (428 °F)

No

64

EPF81188AGI232-A-2

Altera

Loadable PLD

Industrial

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

1.7 ns

No

3.6 V

CMOS

3.3

Grid Array

Registered

3 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 184 I/O

4

-40 °C (-40 °F)

Perpendicular

S-CPGA-P232

5.207 mm

44.7 mm

No

Can also operate at 5 V supply

44.7 mm

184

EPM7192EG5962160-20

Altera

EE PLD

Military

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

20 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 120 I/O

0

-55 °C (-67 °F)

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

62.5 MHz

39.624 mm

120

EPF8820AGC192-2

Altera

Loadable PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

672

No

5.25 V

CMOS

152

5

3.3/5,5 V

Grid Array

PGA192M,17X17

Field Programmable Gate Arrays

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 152 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P192

1

5.43 mm

45.15 mm

No

672 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

417 MHz

148

220 °C (428 °F)

45.15 mm

152

EPF81500AGC280-2A

Altera

Loadable PLD

Commercial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

No

3.6 V

CMOS

3.3

Grid Array

Registered

3 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 208 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P280

1

5.081 mm

49.78 mm

No

220 °C (428 °F)

49.78 mm

208

5962-9316802MXC

Altera

EE PLD

Military

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

2.625 V

192

CMOS

MIL-STD-883

2.5

3.3/5,5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

Macrocell

2.375 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs

0

-55 °C (-67 °F)

Gold

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

e4

76.9 MHz

220 °C (428 °F)

39.624 mm

No

EPM5130GM

Altera

UV PLD

Military

Pin/Peg

100

WPGA

Square

Ceramic, Metal-Sealed Cofired

55 ns

No

5.5 V

128

CMOS

5

5 V

Grid Array, Window

PGA100M,13X13

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

19 Dedicated Inputs, 64 I/O

19

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-CPGA-P100

3.81 mm

33.528 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

e0

33.3 MHz

220 °C (428 °F)

33.528 mm

No

64

EPF81188AGI232-2

Altera

Loadable PLD

Industrial

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

1008

No

5.5 V

CMOS

184

5

3.3/5,5 V

Grid Array

PGA232M,17X17

Field Programmable Gate Arrays

Registered

4.5 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 180 I/O

4

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P232

1

5.207 mm

44.7 mm

No

1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

180

220 °C (428 °F)

44.7 mm

180

EPF8820AGI192-A-3

Altera

Loadable PLD

Industrial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

1.8 ns

No

3.6 V

CMOS

3.3

Grid Array

Registered

3 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 152 I/O

4

-40 °C (-40 °F)

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

Can also operate at 5 V supply

45.15 mm

152

EP1810GC-40

Altera

OT PLD

Commercial

Pin/Peg

68

PGA

Square

Ceramic

45 ns

No

48

CMOS

5

5 V

Grid Array

PGA68,11X11

Programmable Logic Devices

No

2.54 mm

70 °C (158 °F)

0 °C (32 °F)

Tin Lead

Perpendicular

S-XPGA-P68

1

No

e0

220 °C (428 °F)

No

EPF10K30GC403-5

Altera

Loadable PLD

Commercial

Pin/Peg

403

IPGA

Square

Ceramic, Metal-Sealed Cofired

27 ns

No

5.25 V

CMOS

5

Grid Array, Interstitial Pitch

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 248 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P403

3.916 mm

49.78 mm

No

1728 Logic elements Configurable I/O operation with 3.3 V or 5 V

53.76 MHz

49.78 mm

248

EPF81188AGC232-A-3

Altera

Loadable PLD

Commercial

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

1.8 ns

No

3.6 V

CMOS

3.3

Grid Array

Registered

3 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 184 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P232

5.207 mm

44.7 mm

No

Can also operate at 5 V supply

44.7 mm

184

EPF8050MGC560-3

Altera

Loadable PLD

Commercial

Pin/Peg

560

IPGA

Square

Ceramic, Metal-Sealed Cofired

4032

No

5.25 V

CMOS

360

5

5 V

Grid Array, Interstitial Pitch

PGA560,43X43,50

Field Programmable Gate Arrays

Registered

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 360 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P560

1

15.75 mm

60.07 mm

No

4 EPF81188 devices with Field programmable Interconnect; 4656 Flip Flops; 4032 Logic elements

e0

360

220 °C (428 °F)

60.07 mm

360

EPF10K70GC503-4

Altera

Loadable PLD

Commercial

Pin/Peg

503

IPGA

Square

Ceramic, Metal-Sealed Cofired

0.7 ns

3744

No

5.25 V

CMOS

358

5

3.3/5,5 V

Grid Array, Interstitial Pitch

SPGA503,43X43

Field Programmable Gate Arrays

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 358 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P503

1

5.077 mm

57.4 mm

No

3744 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

49 MHz

358

220 °C (428 °F)

57.4 mm

358

EPM5192AGM84-20

Altera

UV PLD

Military

Pin/Peg

84

WPGA

Square

Ceramic, Metal-Sealed Cofired

33 ns

No

5.5 V

CMOS

5

Grid Array, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

7 Dedicated Inputs, 64 I/O

7

-55 °C (-67 °F)

Perpendicular

S-CPGA-P84

4.96 mm

27.94 mm

No

Labs interconnected by PIA; 12 Labs; 1 External Clock

66.7 MHz

27.94 mm

64

EPF10K70GC504-4

Altera

Loadable PLD

Commercial

Pin/Peg

504

PGA

Square

Ceramic, Metal-Sealed Cofired

23.8 ns

No

5.25 V

CMOS

5

Grid Array

Registered

4.75 V

70 °C (158 °F)

4 Dedicated Inputs, 358 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P504

No

3744 Logic elements Configurable I/O operation with 3.3 V or 5 V

60.6 MHz

358

EP1810GC68-45

Altera

UV PLD

Commercial

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

50 ns

No

5.25 V

CMOS

5

Grid Array, Window

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

12 Dedicated Inputs, 48 I/O

12

0 °C (32 °F)

Perpendicular

S-CPGA-P68

4.96 mm

27.94 mm

No

48 Macrocells; Shared Input/Clock

33.3 MHz

27.94 mm

48

5962-9324701MXC

Altera

EE PLD

Military

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

20 ns

No

2.625 V

CMOS

MIL-STD-883

2.5

Grid Array

Macrocell

2.375 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs

0

-55 °C (-67 °F)

Gold

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

e4

62.5 MHz

220 °C (428 °F)

45.15 mm

EPM7256EGC192-10

Altera

EE PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

10 ns

No

5.25 V

256

CMOS

5

3.3/5,5 V

Grid Array

PGA192M,17X17

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 160 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P192

1

5.43 mm

45.15 mm

No

Configurable I/O operation with 3.3 V or 5 V

e0

100 MHz

220 °C (428 °F)

45.15 mm

No

160

EPM7256GC192

Altera

UV PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic

25 ns

No

256

CMOS

5

5 V

Grid Array

PGA192M,17X17

Programmable Logic Devices

No

2.54 mm

70 °C (158 °F)

0 °C (32 °F)

Tin Lead

Perpendicular

S-XPGA-P192

1

No

e0

220 °C (428 °F)

No

EPF10K250AGI599-1

Altera

Loadable PLD

Industrial

Pin/Peg

599

IPGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

3.6 V

CMOS

3.3

Grid Array, Interstitial Pitch

Registered

3 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 470 I/O

4

-40 °C (-40 °F)

Perpendicular

S-CPGA-P599

5.08 mm

62.484 mm

No

62.484 mm

470

EP1810GC68-35

Altera

UV PLD

Commercial

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

40 ns

No

5.25 V

48

CMOS

5

5 V

Grid Array, Window

PGA68,11X11

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

12 Dedicated Inputs, 48 I/O

12

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P68

1

4.96 mm

27.94 mm

No

48 Macrocells; Shared Input/Clock

e0

40 MHz

220 °C (428 °F)

27.94 mm

No

48

EPF10K70GC504-5

Altera

Loadable PLD

Commercial

Pin/Peg

504

PGA

Square

Ceramic, Metal-Sealed Cofired

27 ns

No

5.25 V

CMOS

5

Grid Array

Registered

4.75 V

70 °C (158 °F)

4 Dedicated Inputs, 358 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P504

No

3744 Logic elements Configurable I/O operation with 3.3 V or 5 V

53.76 MHz

358

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.