Pin/Peg Programmable Logic Devices (PLD) 482

Reset All

Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	No. of Logic Cells	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	No. of Inputs	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EPF8820AGC192-3	Altera	Loadable PLD	Commercial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired		672	No	5.25 V		CMOS		152	5	3.3/5,5 V	Grid Array	PGA192M,17X17	Field Programmable Gate Arrays		Registered	4.75 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 152 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	672 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0	385 MHz	148	220 °C (428 °F)	45.15 mm		152
EPM5128AGM68-20	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz			27.94 mm		52
EPM5128AG5962-20	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		66.7 MHz			27.94 mm		52
EP20K400PC655	Altera	Loadable PLD	Other	Pin/Peg	655	IPGA	Square	Ceramic, Metal-Sealed Cofired			No	2.625 V					2.5		Grid Array, Interstitial Pitch				Macrocell	2.375 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 502 I/O	4	0 °C (32 °F)		Perpendicular	S-CPGA-P655		4.08 mm	62.484 mm	No					220 °C (428 °F)	62.484 mm		502
EPM7256EGC192-12	Altera	EE PLD	Commercial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	12 ns		No	5.25 V	256	CMOS			5	3.3/5,5 V	Grid Array	PGA192M,17X17	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 164 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz		220 °C (428 °F)	45.15 mm	No	164
EPM9320GC280-15	Altera	EE PLD	Commercial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	16 ns		No	5.25 V	320	CMOS			5	3.3/5,5 V	Grid Array	PGA280,19X19	Programmable Logic Devices	Yes	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 168 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P280	1	5.081 mm	49.78 mm	No	484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V	e0	117.6 MHz		220 °C (428 °F)	49.78 mm	Yes	168
EPM5128GI-2	Altera	UV PLD	Industrial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.5 V	128	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz		220 °C (428 °F)		No	52
EPM5192GC84-2	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.25 V		CMOS			5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)		Perpendicular	S-CPGA-P84		4.96 mm	28.448 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		40 MHz			28.448 mm		64
EPM5128GI68-2	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	128 Macrocells; 8 Labs		50 MHz			27.94 mm		52
EPM5128GI68	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V	128	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e0	33.3 MHz		220 °C (428 °F)	27.94 mm	No	52
EP1830GC-25	Altera	OT PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic	28 ns		No		48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Perpendicular	S-XPGA-P68	1			No		e0			220 °C (428 °F)		No
EPM9320GM280-12	Altera	EE PLD	Military	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	12 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 168 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	320 Macrocells; 484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz			49.78 mm		168
EPF10K200EGI599-1	Altera	Loadable PLD	Industrial	Pin/Peg	599	IPGA	Square	Ceramic, Metal-Sealed Cofired	10 ns	9984	No	2.7 V		CMOS		470	2.5	2.5,2.5/3.3 V	Grid Array, Interstitial Pitch	SPGA599,47X47	Field Programmable Gate Arrays		Mixed	2.3 V	2.54 mm	85 °C (185 °F)	470 I/O		-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P599	1	5.08 mm	62.484 mm	No		e0		470	220 °C (428 °F)	62.484 mm		470
EPF10K130VGI599-2	Altera	Loadable PLD	Industrial	Pin/Peg	599	IPGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	3.6 V		CMOS			3.3		Grid Array, Interstitial Pitch				Registered	3 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 470 I/O	4	-40 °C (-40 °F)		Perpendicular	S-CPGA-P599		5.08 mm	62.484 mm	No						62.484 mm		470
EPF10K50GC403-3	Altera	Loadable PLD	Commercial	Pin/Peg	403	IPGA	Square	Ceramic, Metal-Sealed Cofired	0.6 ns	2880	No	5.25 V		CMOS		310	5	3.3/5,5 V	Grid Array, Interstitial Pitch	SPGA403M,37X37	Field Programmable Gate Arrays		Registered	4.75 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 310 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P403	1	5.026 mm	49.78 mm	No	2880 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0	66.67 MHz	310	220 °C (428 °F)	49.78 mm		310
EP1800GMB	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	90 ns		No	5.5 V	48	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.0038 mm	27.94 mm	No	48 Macrocells	e0			220 °C (428 °F)	27.94 mm	No	48
EPM5128GM-2	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz			27.94 mm		52
EPM9400GC280-12	Altera	EE PLD	Commercial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	12.6 ns		No	5.25 V	400	CMOS			5	3.3/5,5 V	Grid Array	PGA280,19X19	Programmable Logic Devices	Yes	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 180 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P280	1	5.081 mm	49.78 mm	No	400 Macrocells; 580 Flip Flops Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz		220 °C (428 °F)	49.78 mm	Yes	180
EPF8452AGC160-4	Altera	Loadable PLD	Commercial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired		336	No	5.25 V		CMOS		120	5	3.3/5,5 V	Grid Array	PGA160M,15X15	Field Programmable Gate Arrays		Registered	4.75 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 120 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P160	1	5.34 mm	39.624 mm	No	336 Logic Elements	e0	357 MHz	116	220 °C (428 °F)	39.624 mm		120
EPM5192AGM84-15	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock		83.3 MHz			27.94 mm		64
EPF10K100GC504-5	Altera	Loadable PLD	Commercial	Pin/Peg	504	PGA	Square	Ceramic, Metal-Sealed Cofired	27 ns		No	5.25 V		CMOS			5		Grid Array				Registered	4.75 V		70 °C (158 °F)	4 Dedicated Inputs, 406 I/O	4	0 °C (32 °F)		Perpendicular	S-CPGA-P504				No	4992 Logic elements Configurable I/O operation with 3.3 V or 5 V		53.76 MHz					406
EPM7256EGC192-12PP	Altera	EE PLD	Commercial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	12 ns		No	5.25 V		CMOS			5		Grid Array				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 164 I/O	0	0 °C (32 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No			125 MHz			45.15 mm		164
EPF10K70GM504-5	Altera	Loadable PLD	Military	Pin/Peg	504	PGA	Square	Ceramic, Metal-Sealed Cofired	27 ns		No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V		125 °C (257 °F)	4 Dedicated Inputs, 358 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P504				No	3744 Logic elements Configurable I/O operation with 3.3 V or 5 V		53.76 MHz					358
EP1810GM-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	50 ns		No	5.5 V	48	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	22.2 MHz		220 °C (428 °F)	27.94 mm	No	48
EP1810GC-45	Altera	UV PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	50 ns		No	5.25 V	48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	22.2 MHz		220 °C (428 °F)		No	48
EPF8636AGM192-4	Altera	Loadable PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired			No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 132 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V					45.15 mm		132
EPF8820AGI192-3	Altera	Loadable PLD	Industrial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired		672	No	5.5 V		CMOS		152	5	3.3/5,5 V	Grid Array	PGA192M,17X17	Field Programmable Gate Arrays		Registered	4.5 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 152 I/O	4	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	672 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0	385 MHz	148	220 °C (428 °F)	45.15 mm		152
EPF8452GC160-3	Altera	Loadable PLD	Commercial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired		336	No	5.25 V		CMOS		120	5	3.3/5,5 V	Grid Array	PGA160M,15X15	Field Programmable Gate Arrays		Registered	4.75 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 116 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P160	1	5.34 mm	39.624 mm	No	452 Flip Flops; 336 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0		116	220 °C (428 °F)	39.624 mm		116
EP1810GI68-20	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	22 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		62.5 MHz			27.94 mm		48
EPF81188GM883B232-3	Altera	Loadable PLD	Military	Pin/Peg	232	PGA	Square	Ceramic, Metal-Sealed Cofired			No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 180 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P232		5.207 mm	44.7 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V					44.7 mm		180
EP1800GI-3	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	80 ns		No	5.5 V	48	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	18.5 MHz		220 °C (428 °F)	27.94 mm	No	48
EPF10K200SGI599-1	Altera	Loadable PLD	Industrial	Pin/Peg	599	IPGA	Square	Ceramic, Metal-Sealed Cofired	9 ns	9984	No	2.7 V		CMOS		470	2.5	2.5,2.5/3.3 V	Grid Array, Interstitial Pitch	SPGA599,47X47	Field Programmable Gate Arrays		Mixed	2.3 V	2.54 mm	85 °C (185 °F)	470 I/O		-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P599	1	5.08 mm	62.484 mm	No		e0		470	220 °C (428 °F)	62.484 mm		470
EPF10K200SGI599-2	Altera	Loadable PLD	Industrial	Pin/Peg	599	IPGA	Square	Ceramic, Metal-Sealed Cofired	12 ns	9984	No	2.7 V		CMOS		470	2.5	2.5,2.5/3.3 V	Grid Array, Interstitial Pitch	SPGA599,47X47	Field Programmable Gate Arrays		Mixed	2.3 V	2.54 mm	85 °C (185 °F)	470 I/O		-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P599	1	5.08 mm	62.484 mm	No		e0		470	220 °C (428 °F)	62.484 mm		470
EPF81500AGC280-4	Altera	Loadable PLD	Commercial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	1.9 ns	1296	No	3.6 V		CMOS		208	3.3	3.3/5,5 V	Grid Array	PGA280,19X19	Field Programmable Gate Arrays		Registered	3 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 208 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P280	1	5.081 mm	49.78 mm	No	Can also operate at 5 V supply	e0	357 MHz	204	220 °C (428 °F)	49.78 mm		208
EPM5192GM883B	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No		192	CMOS	38535Q/M;38534H;883B		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P84		4.96 mm	28.45 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz		220 °C (428 °F)	28.45 mm	No	64
EPF10K250AGI599-3	Altera	Loadable PLD	Industrial	Pin/Peg	599	IPGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	3.6 V		CMOS			3.3		Grid Array, Interstitial Pitch				Registered	3 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 470 I/O	4	-40 °C (-40 °F)		Perpendicular	S-CPGA-P599		5.08 mm	62.484 mm	No						62.484 mm		470
5962-01-407-9563	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	35 ns		No		128	CMOS	38535Q/M;38534H;883B		5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)		Perpendicular	S-XPGA-P68				No							No
EP1800GC-1	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	90 ns		No	5.25 V	48	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	25 MHz		220 °C (428 °F)	27.94 mm	No	48
EPF10K30GI403-5	Altera	Loadable PLD	Industrial	Pin/Peg	403	IPGA	Square	Ceramic, Metal-Sealed Cofired	27 ns		No	5.5 V		CMOS			5		Grid Array, Interstitial Pitch				Registered	4.5 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 248 I/O	4	-40 °C (-40 °F)		Perpendicular	S-CPGA-P403		3.916 mm	49.78 mm	No	1728 Logic elements Configurable I/O operation with 3.3 V or 5 V		53.76 MHz			49.78 mm		248
EPM5192GC-1	Altera	UV PLD	Commercial	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	40 ns		No	5.25 V	192	CMOS			5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P84	1			No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e0	50 MHz		220 °C (428 °F)		No	64
EP1810GI-20	Altera	UV PLD	Industrial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.5 V					5		Grid Array				Macrocell	4.5 V		85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68				No			62.5 MHz					48
EPM5128G5962	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz			27.94 mm		52
5962-9324702MXC	Altera	EE PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	2.625 V		CMOS	MIL-STD-883		2.5		Grid Array				Macrocell	2.375 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs	0	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock	e4	76.9 MHz		220 °C (428 °F)	45.15 mm
EPF81188AGC232-2	Altera	Loadable PLD	Commercial	Pin/Peg	232	PGA	Square	Ceramic, Metal-Sealed Cofired		1008	No	5.25 V		CMOS		184	5	3.3/5,5 V	Grid Array	PGA232M,17X17	Field Programmable Gate Arrays		Registered	4.75 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 184 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P232	1	5.207 mm	44.7 mm	No	1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0	417 MHz	180	220 °C (428 °F)	44.7 mm		184
EPM5192GI-1	Altera	UV PLD	Industrial	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	25 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V		85 °C (185 °F)	7 Dedicated Inputs, 64 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P84				No		e0	62.5 MHz					64
EPF10K50GI403-4	Altera	Loadable PLD	Industrial	Pin/Peg	403	IPGA	Square	Ceramic, Metal-Sealed Cofired	21.1 ns	2880	No	5.25 V		CMOS		310	5	3.3/5,5 V	Grid Array, Interstitial Pitch	SPGA403M,37X37	Field Programmable Gate Arrays		Registered	4.75 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 310 I/O	4	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P403	1	5.026 mm	49.78 mm	No	2880 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0	62.89 MHz	310	220 °C (428 °F)	49.78 mm		310
EPF8820GI192-2	Altera	Loadable PLD	Industrial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired			No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 148 I/O	4	-40 °C (-40 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V					45.15 mm		148
EPM7256SGC192-10	Altera	EE PLD	Commercial	Pin/Peg	192	PGA	Square	Ceramic	10 ns		No		256	CMOS				3.3/5,5 V	Grid Array	PGA192M,17X17	Programmable Logic Devices	Yes			2.54 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Perpendicular	S-XPGA-P192	1			No		e0			220 °C (428 °F)		Yes

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.