Pin/Peg Programmable Logic Devices (PLD) 482

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	No. of Logic Cells	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	No. of Inputs	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EPM7256EGM883B192-20	Altera	EE PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 160 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock		62.5 MHz			45.15 mm		160
EPM7256GC192-20	Altera	UV PLD	Commercial	Pin/Peg	192	WPGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.25 V	256	CMOS			5	5 V	Grid Array, Window	PGA192M,17X17	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 160 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	256 Macrocells; Shared Input/Clock	e0	62.5 MHz		220 °C (428 °F)	45.15 mm	No	160
EPM7192EGM883B160-15	Altera	EE PLD	Military	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 120 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P160		5.34 mm	39.624 mm	No	192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock		76.9 MHz			39.624 mm		120
EPF8820G5962192-3	Altera	Loadable PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired			No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 148 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V					45.15 mm		148
EPM7192EGM883B160-20	Altera	EE PLD	Military	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 120 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P160		5.34 mm	39.624 mm	No	192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock		62.5 MHz			39.624 mm		120
EPM9320GI280-20	Altera	EE PLD	Industrial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	23 ns		No	5.5 V	320	CMOS			5	3.3/5,5 V	Grid Array	PGA280,19X19	Programmable Logic Devices	Yes	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 168 I/O	0	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P280	1	5.08 mm	49.78 mm	No	484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V	e0	100 MHz		220 °C (428 °F)	49.78 mm	Yes	168
EPM5192G5962-2	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz			27.94 mm		64
EPM7192EGM160-15	Altera	EE PLD	Military	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No		192	CMOS			5	3.3/5,5 V	Grid Array	PGA160M,15X15	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	0 Dedicated Inputs	0	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P160		5.34 mm	39.624 mm	No	192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock	e0	76.9 MHz		220 °C (428 °F)	39.624 mm	No
EP20K1000EPC984-2	Altera	Loadable PLD	Other	Pin/Peg	984	PGA	Square	Ceramic, Metal-Sealed Cofired			No	1.89 V					1.8		Grid Array				Macrocell	1.71 V		85 °C (185 °F)	4 Dedicated Inputs, 716 I/O	4	0 °C (32 °F)		Perpendicular	S-CPGA-P984				No			160 MHz					716
5962-9206202MYC	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.5 V		CMOS	MIL-STD-883		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P84		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e4	40 MHz			27.94 mm		64
EPM5192GM883B-2	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No		192	CMOS	MIL-STD-883 Class B (Modified)		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P84		4.96 mm	28.45 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz		220 °C (428 °F)	28.45 mm	No	64
EPM7192EGI160-10	Altera	EE PLD	Industrial	Pin/Peg	160	PGA	Square	Ceramic	10 ns		No		192	CMOS				3.3/5,5 V	Grid Array	PGA160M,15X15	Programmable Logic Devices	No			2.54 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Perpendicular	S-XPGA-P160	1			No		e0			220 °C (428 °F)		No
EPM5128AGC-20	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns		No	5.25 V	128	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	66.7 MHz		220 °C (428 °F)	27.94 mm	No	52
5962-9314402MZC	Altera	UV PLD	Military	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.5 V		CMOS	MIL-STD-883		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P100		3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e4	40 MHz			33.528 mm		64
EPM7256EGI192-12	Altera	EE PLD	Industrial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	12 ns		No	5.5 V	256	CMOS			5	3.3/5,5 V	Grid Array	PGA192M,17X17	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 164 I/O	0	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	256 Macrocells	e0	125 MHz		220 °C (428 °F)	45.15 mm	No	164
EPM5192GC-2	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.25 V	192	CMOS			5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P84	1	4.96 mm	28.45 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e0	50 MHz		220 °C (428 °F)	28.45 mm	No	64
EP20K1500EPC984	Altera	Loadable PLD	Other	Pin/Peg	984	PGA	Square	Ceramic, Metal-Sealed Cofired			No	1.89 V					1.8		Grid Array				Macrocell	1.71 V		85 °C (185 °F)	4 Dedicated Inputs, 858 I/O	4	0 °C (32 °F)		Perpendicular	S-CPGA-P984				No			160 MHz					858
EPM5128AGC68-12	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.25 V		CMOS			5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz			27.94 mm		52
EPM7192EGI160-15	Altera	EE PLD	Industrial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	5.5 V	192	CMOS			5	3.3/5,5 V	Grid Array	PGA160M,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 120 I/O	0	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P160	1	5.34 mm	39.624 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	76.9 MHz		220 °C (428 °F)	39.624 mm	No	120
EPM5130GI	Altera	UV PLD	Industrial	Pin/Peg	100	PGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V	128	CMOS			5	5 V	Grid Array	PGA100M,13X13	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	19 Dedicated Inputs, 64 I/O	19	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P100	1			No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz		220 °C (428 °F)		No	64
EPF10K100GI504-4	Altera	Loadable PLD	Industrial	Pin/Peg	504	PGA	Square	Ceramic, Metal-Sealed Cofired	23.8 ns		No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V		85 °C (185 °F)	4 Dedicated Inputs, 406 I/O	4	-40 °C (-40 °F)		Perpendicular	S-CPGA-P504				No	4992 Logic elements Configurable I/O operation with 3.3 V or 5 V		60.6 MHz					406
EP1810GM5962-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	50 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	48 Macrocells; 4 External Clocks; Shared Input/Clock		22.2 MHz			27.94 mm		48
EPM9560GM280-15	Altera	EE PLD	Military	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 216 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		117.6 MHz			49.78 mm		216
EPF10K50GM403-4	Altera	Loadable PLD	Military	Pin/Peg	403	IPGA	Square	Ceramic, Metal-Sealed Cofired	23.8 ns		No	5.5 V		CMOS			5		Grid Array, Interstitial Pitch				Registered	4.5 V	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 310 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P403		3.916 mm	49.78 mm	No	2880 Logic elements Configurable I/O operation with 3.3 V or 5 V		60.6 MHz			49.78 mm		310
EPF10K250AGC599-1	Altera	Loadable PLD	Commercial	Pin/Peg	599	IPGA	Square	Ceramic, Metal-Sealed Cofired	0.5 ns	12160	No	3.6 V		CMOS		470	3.3	2.5/3.3,3.3 V	Grid Array, Interstitial Pitch	SPGA599,47X47	Field Programmable Gate Arrays		Registered	3 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 470 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P599	1	5.08 mm	62.484 mm	No	12160 Logic Elements; 1520 Labs	e0	80 MHz	470	220 °C (428 °F)	62.484 mm		470
EPM5128GM68	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz			27.94 mm		52
EPM9480GI280-15	Altera	EE PLD	Industrial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 200 I/O	0	-40 °C (-40 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	480 Macrocells; 676 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz			49.78 mm		200
EPF8452AGC160-A-2	Altera	Loadable PLD	Commercial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	1.7 ns		No	3.6 V		CMOS			3.3		Grid Array				Registered	3 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 120 I/O	4	0 °C (32 °F)		Perpendicular	S-CPGA-P160		5.34 mm	39.624 mm	No	Can also operate at 5 V supply					39.624 mm		120
EPM9480GM280-15	Altera	EE PLD	Military	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 200 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	480 Macrocells; 676 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz			49.78 mm		200
EP20K400GC655-1	Altera	Loadable PLD	Other	Pin/Peg	655	PGA	Square	Ceramic, Metal-Sealed Cofired	2.5 ns	16640	No	2.625 V		CMOS		496	2.5	2.5,2.5/3.3 V	Grid Array	SPGA655,47X47	Field Programmable Gate Arrays		Macrocell	2.375 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 502 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P655	1	4.08 mm	62.484 mm	No		e0		496	220 °C (428 °F)	62.484 mm		502
EPM5128AGI68-15	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		83.3 MHz			27.94 mm		52
EPM7192GC160-20	Altera	EE PLD	Commercial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.25 V	192	CMOS			5	5 V	Grid Array	PGA160M,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 120 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P160	1	5.34 mm	39.624 mm	No	192 Macrocells; Shared Input/Clock	e0	62.5 MHz		220 °C (428 °F)	39.624 mm	No	120
EPM5130GI100	Altera	UV PLD	Industrial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	19 Dedicated Inputs, 64 I/O	19	-40 °C (-40 °F)		Perpendicular	S-CPGA-P100		4.96 mm	33.528 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz			33.528 mm		64
MPM5130GC-1	Altera	Mask PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns		No	5.25 V		CMOS			5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100	1	4.953 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz		220 °C (428 °F)	33.528 mm		64
EPF81500AGC280-2	Altera	Loadable PLD	Commercial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	1.7 ns	1296	No	3.6 V		CMOS		208	3.3	3.3/5,5 V	Grid Array	PGA280,19X19	Field Programmable Gate Arrays		Registered	3 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 208 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P280	1	5.081 mm	49.78 mm	No	Can also operate at 5 V supply	e0	417 MHz	204	220 °C (428 °F)	49.78 mm		208
EPM5130GI-2	Altera	UV PLD	Industrial	Pin/Peg	100	PGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V		85 °C (185 °F)	19 Dedicated Inputs, 64 I/O	19	-40 °C (-40 °F)		Perpendicular	S-CPGA-P100				No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz					64
EPM5192GM84	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		4.96 mm	27.94 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz			27.94 mm		64
EPF8636AGC192-A-3	Altera	Loadable PLD	Commercial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	1.8 ns		No	3.6 V		CMOS			3.3		Grid Array				Registered	3 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 136 I/O	4	0 °C (32 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	Can also operate at 5 V supply					45.15 mm		136
EPM9560GM280-20	Altera	EE PLD	Military	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 216 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		95.2 MHz			49.78 mm		216
EP1830GC-30	Altera	OT PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic	34 ns		No		48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Perpendicular	S-XPGA-P68	1			No		e0			220 °C (428 °F)		No
EPM5128AGM68-12	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz			27.94 mm		52
EP1810GI68-35	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		40 MHz			27.94 mm		48
EP1800GM	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	90 ns		No		48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Perpendicular	S-XPGA-P68				No		e0			220 °C (428 °F)		No
EPF8820GM883B192-3	Altera	Loadable PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired			No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 148 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V					45.15 mm		148
EPF81188AGI232-4	Altera	Loadable PLD	Industrial	Pin/Peg	232	PGA	Square	Ceramic, Metal-Sealed Cofired		1008	No	5.5 V		CMOS		184	5	3.3/5,5 V	Grid Array	PGA232M,17X17	Field Programmable Gate Arrays		Registered	4.5 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 180 I/O	4	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P232	1	5.207 mm	44.7 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0		180	220 °C (428 °F)	44.7 mm		180
5962-9314401MYC	Altera	UV PLD	Military	Pin/Peg	100	PGA	Square	Ceramic, Metal-Sealed Cofired	75 ns		No	5.5 V		CMOS	MIL-STD-883 Class B		5		Grid Array				Macrocell	4.5 V		125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)		Perpendicular	S-CPGA-P100				No			22.2 MHz					64
5962-01-407-9563	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	35 ns		No		128	CMOS	38535Q/M;38534H;883B		5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)		Perpendicular	S-XPGA-P68				No							No
EP1800GC-1	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	90 ns		No	5.25 V	48	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	25 MHz		220 °C (428 °F)	27.94 mm	No	48

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.