WPGA Programmable Logic Devices (PLD) 120

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
CY7C342B-30RI	Cypress Semiconductor	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	60 ns	No	5.5 V	128	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	27.7 MHz		27.9527 mm	No	52
5962-8946804XA	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	42 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz		27.9527 mm		52
5962-8946803XA	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	51 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz		27.9527 mm		52
5962-8946804XX	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	42 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz		27.9527 mm		52
5962-8946805XA	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	50 MHz		27.9527 mm		52
5962-8946805XX	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz		27.9527 mm		52
XC73108-10PG144C	Xilinx	UV PLD	Commercial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.25 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		62.5 MHz		39.624 mm	No	78
XC73108-20PG144I	Xilinx	UV PLD	Industrial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 78 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz		39.624 mm	No	78
XC73108-7PG144C	Xilinx	UV PLD	Commercial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	18 ns	No	5.25 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		83.3 MHz		39.624 mm	No	78
XC7272A-16PG84I	Xilinx	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.5 V	72	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 42 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		55 MHz		27.94 mm	No	42
XC73108-12PG144I	Xilinx	UV PLD	Industrial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	30 ns	No	5.5 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 78 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		55.6 MHz		39.624 mm	No	78
XC7272A-20PG84I	Xilinx	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	32 ns	No	5.5 V	72	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 42 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		50 MHz		27.94 mm	No	42
XC7272A-16PG84C	Xilinx	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.25 V	72	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 42 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		55 MHz		27.94 mm	No	42
XC7272A-25PG84C	Xilinx	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.25 V	72	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 42 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz		27.94 mm	No	42
XC73108-20PG144M	Xilinx	UV PLD	Military	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 78 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz		39.624 mm	No	78
XC73108-15PG144M	Xilinx	UV PLD	Military	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.5 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 78 I/O	12	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P144		3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops	e0	45.5 MHz		39.624 mm	No	78
XC7272A-20PG84C	Xilinx	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	32 ns	No	5.25 V	72	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 42 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		50 MHz		27.94 mm	No	42
XC73108-12PG144C	Xilinx	UV PLD	Commercial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	30 ns	No	5.25 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		55.6 MHz		39.624 mm	No	78
XC7272A-25PG84I	Xilinx	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.5 V	72	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 42 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz		27.94 mm	No	42
XC73108-15PG144I	Xilinx	UV PLD	Industrial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.5 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 78 I/O	12	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P144		3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops	e0	45.5 MHz		39.624 mm	No	78
XC73108-20PG144C	Xilinx	UV PLD	Commercial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.25 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz		39.624 mm	No	78
XC73108-15PG144C	Xilinx	UV PLD	Commercial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.25 V	108	CMOS		5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		45.5 MHz		39.624 mm	No	78
EPM5130AGC-15	Altera	UV PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100		3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		83.3 MHz		33.528 mm		64
EPM5192GC84-2	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)		Perpendicular	S-CPGA-P84		4.96 mm	28.448 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		40 MHz		28.448 mm		64
EPM5128GI68-2	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	128 Macrocells; 8 Labs		50 MHz		27.94 mm		52
EPM5128GI68	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V	128	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e0	33.3 MHz	220 °C (428 °F)	27.94 mm	No	52
EP1800GC-3	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	80 ns	No	5.25 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	18.5 MHz	220 °C (428 °F)	27.94 mm	No	48
EPM5192GC84-1	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.25 V	192	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P84	1	4.96 mm	28.448 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms	e0	50 MHz	220 °C (428 °F)	28.448 mm	No	64
EPM5192GM	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No		192	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P84		4.96 mm	28.45 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz	220 °C (428 °F)	28.45 mm	No	64
EPM5130GC100	Altera	UV PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.25 V	128	CMOS		5	5 V	Grid Array, Window	PGA100M,13X13	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P100	1	4.96 mm	33.528 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e0	33.3 MHz	220 °C (428 °F)	33.528 mm	No	64
EPM5130GM-2	Altera	UV PLD	Military	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)		Perpendicular	S-CPGA-P100		3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz		33.528 mm		64
EPM5192GC84	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.25 V	192	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P84	1	4.96 mm	28.448 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms	e0	33.3 MHz	220 °C (428 °F)	28.448 mm	No	64
EPM5192AGC84-15	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.25 V	192	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P84	1	4.96 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock	e0	83.3 MHz	220 °C (428 °F)	27.94 mm	No	64
EP1800GC-2	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	70 ns	No	5.25 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	20.8 MHz	220 °C (428 °F)	27.94 mm	No	48
EPM5128GC68-1	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.25 V	128	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e0	50 MHz	220 °C (428 °F)	27.94 mm	No	52
EPM5130G5962	Altera	UV PLD	Military	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)		Perpendicular	S-CPGA-P100		3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz		33.528 mm		64
EPM5192AGC84-20	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.25 V	192	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P84	1	4.96 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock	e0	66.7 MHz	220 °C (428 °F)	27.94 mm	No	64
EPM5192G5962	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz		27.94 mm		64
EP1810GM883B68-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		22.2 MHz		27.94 mm		48
EPM5192AGI84-20	Altera	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 64 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock		66.7 MHz		27.94 mm		64
EPM5128GM5962	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz		27.94 mm		52
EPM5192GI84-1	Altera	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 64 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		4.96 mm	28.448 mm	No	192 Macrocells; 12 Labs		62.5 MHz		28.448 mm		64
EPM5128GC-2	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.25 V	128	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	50 MHz	220 °C (428 °F)	27.94 mm	No	52
EP1810G5962-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks		22.2 MHz		27.94 mm		48
EPM5128GC	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.25 V	128	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz	220 °C (428 °F)	27.94 mm	No	52
5962-9206201MYC	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS	MIL-STD-883	5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P84		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e4	33.3 MHz		27.94 mm		64
EPM7256GC192-25	Altera	UV PLD	Commercial	Pin/Peg	192	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.25 V	256	CMOS		5	5 V	Grid Array, Window	PGA192M,17X17	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 160 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	256 Macrocells; Shared Input/Clock	e0	40 MHz	220 °C (428 °F)	45.15 mm	No	160
EP1800GMB	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	90 ns	No	5.5 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.0038 mm	27.94 mm	No	48 Macrocells	e0		220 °C (428 °F)	27.94 mm	No	48

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.