WPGA Programmable Logic Devices (PLD) 120

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EPM5128AGI68-15	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		83.3 MHz		27.94 mm		52
EPM5130GI100	Altera	UV PLD	Industrial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	19 Dedicated Inputs, 64 I/O	19	-40 °C (-40 °F)		Perpendicular	S-CPGA-P100		4.96 mm	33.528 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz		33.528 mm		64
MPM5130GC-1	Altera	Mask PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100	1	4.953 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz	220 °C (428 °F)	33.528 mm		64
EPM5192GM84	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		4.96 mm	27.94 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz		27.94 mm		64
EPM5128AGM68-12	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	20 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz		27.94 mm		52
EP1810GI68-35	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		40 MHz		27.94 mm		48
5962-8946901YX	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V	48	CMOS	38535Q/M;38534H;883B	5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e4	22.2 MHz	220 °C (428 °F)	27.94 mm	No	48
EPM5128AGM68-20	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz		27.94 mm		52
EPM5128AG5962-20	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		66.7 MHz		27.94 mm		52
EPM5192GC84-2	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)		Perpendicular	S-CPGA-P84		4.96 mm	28.448 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		40 MHz		28.448 mm		64
EPM5128GI68-2	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	128 Macrocells; 8 Labs		50 MHz		27.94 mm		52
EPM5128GI68	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V	128	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e0	33.3 MHz	220 °C (428 °F)	27.94 mm	No	52
EP1800GMB	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	90 ns	No	5.5 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.0038 mm	27.94 mm	No	48 Macrocells	e0		220 °C (428 °F)	27.94 mm	No	48
EPM5128GM-2	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz		27.94 mm		52
EPM5192AGM84-15	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock		83.3 MHz		27.94 mm		64
EP1810GM-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	50 ns	No	5.5 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	22.2 MHz	220 °C (428 °F)	27.94 mm	No	48
EP1810GI68-20	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	22 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		62.5 MHz		27.94 mm		48
EP1800GI-3	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	80 ns	No	5.5 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	18.5 MHz	220 °C (428 °F)	27.94 mm	No	48
EPM5192GM883B	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No		192	CMOS	38535Q/M;38534H;883B	5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P84		4.96 mm	28.45 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz	220 °C (428 °F)	28.45 mm	No	64
EP1800GC-1	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	90 ns	No	5.25 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	25 MHz	220 °C (428 °F)	27.94 mm	No	48
EPM5128G5962	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz		27.94 mm		52
EPM5128AGC68-15	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		83.3 MHz		27.94 mm		52
EP1810GM68-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	50 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		22.2 MHz		27.94 mm		48
EP1810GI68-45	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	50 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		33.3 MHz		27.94 mm		48
EPM5128GC68	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.25 V	128	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e0	33.3 MHz	220 °C (428 °F)	27.94 mm	No	52
EP1800GI-2	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	70 ns	No	5.5 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	20.8 MHz	220 °C (428 °F)	27.94 mm	No	48
MPM5130GC	Altera	Mask PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100	1	4.953 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz	220 °C (428 °F)	33.528 mm		64
5962-8946901YC	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e4	22.2 MHz		27.94 mm		48
EPM5192AGI84-15	Altera	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 64 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock		83.3 MHz		27.94 mm		64
EPM5130GM883B-2	Altera	UV PLD	Military	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V	128	CMOS	38535Q/M;38534H;883B	5	5 V	Grid Array, Window	PGA100M,13X13	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P100		3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz	220 °C (428 °F)	33.528 mm	No	64
EPM5192AGC84-20	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.25 V	192	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P84	1	4.96 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock	e0	66.7 MHz	220 °C (428 °F)	27.94 mm	No	64
EPM5192G5962	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz		27.94 mm		64
EPM5130G5962-2	Altera	UV PLD	Military	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)		Perpendicular	S-CPGA-P100		3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz		33.528 mm		64
EPM5128AGM68-15	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		83.3 MHz		27.94 mm		52
EP1810GM883B68-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		22.2 MHz		27.94 mm		48
EPM5192AGI84-20	Altera	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 64 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock		66.7 MHz		27.94 mm		64
EPM5128GM5962	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz		27.94 mm		52
EPM5192GI84-1	Altera	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 64 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		4.96 mm	28.448 mm	No	192 Macrocells; 12 Labs		62.5 MHz		28.448 mm		64
EPM5130GC100-2	Altera	UV PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100		4.96 mm	33.528 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		40 MHz		33.528 mm		64
EP1800GC-3	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	80 ns	No	5.25 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	18.5 MHz	220 °C (428 °F)	27.94 mm	No	48
EPM5192GC84-1	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.25 V	192	CMOS		5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P84	1	4.96 mm	28.448 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms	e0	50 MHz	220 °C (428 °F)	28.448 mm	No	64
EPM5130AGC-15	Altera	UV PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100		3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		83.3 MHz		33.528 mm		64
EPM5128AGI68-12	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	20 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz		27.94 mm		52
5962-8946801XC	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No		128	CMOS	MIL-STD-883	5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e4	33.3 MHz	220 °C (428 °F)	27.94 mm	No	52
5962-8946801XX	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No		128	CMOS	MIL-STD-883	5		Grid Array, Window				Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz		27.94 mm		52
EPM5128GM883B-2	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No		128	CMOS	38535Q/M;38534H;883B	5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz	220 °C (428 °F)	27.94 mm	No	52
EP1810GC68-25	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	28 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		50 MHz		27.94 mm		48
EP1810GM883B-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks		22.2 MHz		27.94 mm		48

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.