Military Programmable Logic Devices (PLD) 1,614

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	No. of Inputs	Architecture	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	No. of Product Terms	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EP610DM24-35	Altera	UV PLD	Military	Through-Hole	24	WDIP	Rectangular	Ceramic, Glass-Sealed	37 ns	No	5.5 V		CMOS				5		In-Line, Window				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)		Dual	R-GDIP-T24	5.08 mm	7.62 mm	No	16 Macrocells; 2 External Clocks		28.6 MHz			32 mm		16
EPM5128ALM68-15	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Plastic/Epoxy	25 ns	Yes	5.5 V		CMOS				5		Chip Carrier				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-PQCC-J68	5.08 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		83.3 MHz			24.2316 mm		52
EPM7256EWM208-20	Altera	EE PLD	Military	Gull Wing	208	QFP	Square	Ceramic	20 ns	Yes		256	CMOS				5	3.3/5,5 V	Flatpack	QFP208,1.2SQ,20	Programmable Logic Devices	No	Macrocell			.5 mm	125 °C (257 °F)	0 Dedicated Inputs	0	-55 °C (-67 °F)	Tin Lead	Quad	S-XQFP-G208			No		e0			220 °C (428 °F)		No
EP610JM883BX-35	Altera	UV PLD	Military	J Bend	28	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	37 ns	Yes	5.5 V		CMOS				5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)		Quad	S-CQCC-J28	4.826 mm	11.43 mm	No	Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks		28.6 MHz			11.43 mm		16
5962-9324701MXX	Altera	EE PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns	No	2.625 V		CMOS	MIL-STD-883			2.5		Grid Array				Macrocell	2.375 V		2.54 mm	125 °C (257 °F)	0 Dedicated Inputs	0	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P192	5.43 mm	45.15 mm	No	256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock	e4	62.5 MHz			45.15 mm
EPM5128AJM68-12	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	20 ns	Yes	5.5 V		CMOS				5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-CQCC-J68	5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz			24.13 mm		52
EPF8452ALM84-6	Altera	Loadable PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Chip Carrier				Registered	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 64 I/O	4	-55 °C (-67 °F)		Quad	S-PQCC-J84	5.08 mm	29.3116 mm	No	452 Flip Flops; 336 Logic Elements					29.3116 mm		64
EPF8820GM192-2	Altera	Loadable PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired		No	5.5 V		CMOS				5		Grid Array				Registered	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 148 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P192	5.43 mm	45.15 mm	No	820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V					45.15 mm		148
EPF8452AGM160-4	Altera	Loadable PLD	Military	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired		No	5.5 V		CMOS				5		Grid Array				Registered	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 116 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P160	5.34 mm	39.624 mm	No	452 Flip Flops; 336 Logic Elements					39.624 mm		116
EP630DM-20	Altera		Military	Through-Hole	24	DIP	Rectangular	Ceramic	22 ns	No			CMOS		20	PAL-TYPE	5	5 V	In-Line	DIP24,.3	Programmable Logic Devices		Macrocell		160	2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Dual	R-XDIP-T24			No		e0	55.5 MHz	16	220 °C (428 °F)
EPM5130G5962	Altera	UV PLD	Military	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS				5		Grid Array, Window				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)		Perpendicular	S-CPGA-P100	3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz			33.528 mm		64
EP600DM	Altera	UV PLD	Military	Through-Hole	24	WDIP	Rectangular	Ceramic, Glass-Sealed	55 ns	No	5.5 V		CMOS		20	PAL-TYPE	5	5 V	In-Line, Window	DIP24,.3	Programmable Logic Devices		Macrocell	4.5 V	160	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)	Tin Lead	Dual	R-GDIP-T24	4.826 mm	7.62 mm	No	16 Macrocells	e0	22.2 MHz	16	220 °C (428 °F)	31.9405 mm		16
EPF81188ARM240-5	Altera	Loadable PLD	Military	Gull Wing	240	HFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 180 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G240	4.1 mm	32 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e3				32 mm		180
EPM5032JM	Altera	UV PLD	Military	J Bend	28	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns	Yes			CMOS		24	PAL-TYPE	5	5 V	Chip Carrier, Window	LDCC28,.5SQ	Programmable Logic Devices		Macrocell		320	1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 16 I/O	7	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J28	4.57 mm	11.43 mm	No		e0	62.5 MHz	16	220 °C (428 °F)	11.43 mm		16
EP610ASM-10	Altera	OT PLD	Military	Gull Wing	24	SOP	Rectangular	Plastic/Epoxy	10 ns	Yes	5.5 V		CMOS				5		Small Outline				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)		Dual	R-PDSO-G24	2.65 mm	7.5 mm	No	Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks		100 MHz			15.4 mm		16
EPF10K70BM560-5	Altera	Loadable PLD	Military	Ball	560	BGA	Square	Plastic/Epoxy	27 ns	Yes	5.5 V		CMOS				5		Grid Array				Registered	4.5 V			125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)	Tin Silver Copper	Bottom	S-PBGA-B560			No	3744 Logic elements Configurable I/O operation with 3.3 V or 5 V	e1	53.76 MHz
5962-9314401MXA	Altera	UV PLD	Military	Gull Wing	100	WQFP	Rectangular	Ceramic, Metal-Sealed Cofired	55 ns	Yes	5.5 V		CMOS	MIL-STD-883			5		Flatpack, Window				Macrocell	4.5 V		.65 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)	Tin Lead	Quad	R-CQFP-G100	2.99 mm	14 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz			19.2 mm		64
EP910JM883B-40	Altera	UV PLD	Military	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	43 ns	Yes	5.5 V		CMOS				5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 24 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J44	4.826 mm	16.51 mm	No	Macrocells Interconnected By Global Bus; 24 Macrocells; 2 External Clocks		25 MHz			16.51 mm		24
EP1810G5962-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS				5		Grid Array, Window				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68	3.81 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks		22.2 MHz			27.94 mm		48
EPM7192EGM160-20	Altera	EE PLD	Military	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns	No	5.5 V	192	CMOS				5	3.3/5,5 V	Grid Array	PGA160M,15X15	Programmable Logic Devices	No	Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 120 I/O	0	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P160	5.34 mm	39.624 mm	No	192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock	e0	62.5 MHz		220 °C (428 °F)	39.624 mm	No	120
EP910JM-45	Altera		Military	J Bend	44	QCCJ	Square	Ceramic		Yes			CMOS		36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell		240	1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-XQCC-J44			No		e0	22.2 MHz	24	220 °C (428 °F)
EPF10K50GM403-5	Altera	Loadable PLD	Military	Pin/Peg	403	IPGA	Square	Ceramic, Metal-Sealed Cofired	27 ns	No	5.5 V		CMOS				5		Grid Array, Interstitial Pitch				Registered	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 310 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P403	3.916 mm	49.78 mm	No	2880 Logic elements Configurable I/O operation with 3.3 V or 5 V		53.76 MHz			49.78 mm		310
EPF8636ARM208-5	Altera	Loadable PLD	Military	Gull Wing	208	HFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 132 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G208	4.1 mm	28 mm	No	636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e3				28 mm		132
5962-9324702MXX	Altera	EE PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns	No	2.625 V		CMOS	MIL-STD-883			2.5		Grid Array				Macrocell	2.375 V		2.54 mm	125 °C (257 °F)	0 Dedicated Inputs	0	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P192	5.43 mm	45.15 mm	No	256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock	e4	76.9 MHz			45.15 mm
5962-9206201MYC	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS	MIL-STD-883			5		Grid Array, Window				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P84	3.81 mm	27.94 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e4	33.3 MHz			27.94 mm		64
EPF8452AGM160-6	Altera	Loadable PLD	Military	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired		No	5.5 V		CMOS				5		Grid Array				Registered	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 116 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P160	5.34 mm	39.624 mm	No	452 Flip Flops; 336 Logic Elements					39.624 mm		116
5962-9316802MXX	Altera	EE PLD	Military	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns	No	2.625 V		CMOS	MIL-STD-883			2.5		Grid Array				Macrocell	2.375 V		2.54 mm	125 °C (257 °F)	0 Dedicated Inputs	0	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P160	5.34 mm	39.624 mm	No	192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock	e4	76.9 MHz			39.624 mm
EPF8636ARM208-4	Altera	Loadable PLD	Military	Gull Wing	208	HFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 132 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G208	4.1 mm	28 mm	No	636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e3				28 mm		132
EPF81188AGM232-6	Altera	Loadable PLD	Military	Pin/Peg	232	PGA	Square	Ceramic, Metal-Sealed Cofired		No	5.5 V		CMOS				5		Grid Array				Registered	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 180 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P232	5.207 mm	44.7 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V					44.7 mm		180
EPF8282TM100-3	Altera	Loadable PLD	Military	Gull Wing	100	LFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Low Profile, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 74 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G100	1.27 mm	14 mm	No	282 Flip Flops; 208 Logic elements; Built-in JTAG boundry-scan test circuitry	e3				14 mm		74

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.