Part | RoHS | Manufacturer | Programmable IC Type | Grading Of Temperature | Form Of Terminal | No. of Terminals | Package Code | Package Shape | Package Body Material | Propagation Delay | No. of Logic Cells | Surface Mount | Maximum Supply Voltage | No. of Macro Cells | Technology Used | Screening Level | No. of Inputs | Architecture | Nominal Supply Voltage (V) | Packing Method | Power Supplies (V) | Package Style (Meter) | Package Equivalence Code | Sub-Category | In-System Programmable | Output Function | Minimum Supply Voltage | No. of Product Terms | Pitch Of Terminal | Maximum Operating Temperature | Organization | No. of Dedicated Inputs | Minimum Operating Temperature | Finishing Of Terminal Used | Position Of Terminal | JESD-30 Code | Moisture Sensitivity Level (MSL) | Maximum Seated Height | Width | Qualification | Additional Features | JESD-609 Code | Maximum Clock Frequency | Maximum Time At Peak Reflow Temperature (s) | No. of Outputs | Peak Reflow Temperature (C) | Length | JTAG Boundary Scan Test | No. of I/O Lines |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
WPGA |
Square |
Ceramic, Metal-Sealed Cofired |
50 ns |
No |
5.5 V |
48 |
CMOS |
5 |
5 V |
Grid Array, Window |
PGA68,11X11 |
Programmable Logic Devices |
No |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
12 Dedicated Inputs, 48 I/O |
12 |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-CPGA-P68 |
3.81 mm |
27.94 mm |
No |
Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks |
e0 |
22.2 MHz |
220 °C (428 °F) |
27.94 mm |
No |
48 |
|||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
192 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 132 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P192 |
5.43 mm |
45.15 mm |
No |
636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
45.15 mm |
132 |
||||||||||||||||||||||
Altera |
OT PLD |
Military |
Gull Wing |
24 |
SOP |
Rectangular |
Plastic/Epoxy |
37 ns |
Yes |
5.5 V |
CMOS |
5 |
Small Outline |
Macrocell |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 16 I/O |
4 |
-55 °C (-67 °F) |
Dual |
R-PDSO-G24 |
2.65 mm |
7.5 mm |
No |
16 Macrocells; 2 External Clocks |
28.6 MHz |
15.4 mm |
16 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
232 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 180 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P232 |
5.207 mm |
44.7 mm |
No |
1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
44.7 mm |
180 |
||||||||||||||||||||||
Altera |
OT PLD |
Military |
J Bend |
68 |
QCCJ |
Square |
Ceramic |
50 ns |
Yes |
48 |
CMOS |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Programmable Logic Devices |
No |
1.27 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-XQCC-J68 |
e0 |
220 °C (428 °F) |
No |
|||||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
84 |
WPGA |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
No |
192 |
CMOS |
38535Q/M;38534H;883B |
5 |
5 V |
Grid Array, Window |
PGA84M,11X11 |
Programmable Logic Devices |
No |
Macrocell |
2.54 mm |
125 °C (257 °F) |
7 Dedicated Inputs, 64 I/O |
7 |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-CPGA-P84 |
4.96 mm |
28.45 mm |
No |
Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock |
e0 |
33.3 MHz |
220 °C (428 °F) |
28.45 mm |
No |
64 |
||||||||||||
Altera |
EE PLD |
Military |
Gull Wing |
208 |
HFQFP |
Square |
Plastic/Epoxy |
25 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug, Fine Pitch |
Macrocell |
4.5 V |
.5 mm |
125 °C (257 °F) |
0 Dedicated Inputs, 153 I/O |
0 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G208 |
4.1 mm |
28 mm |
No |
560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V |
e3 |
66.7 MHz |
28 mm |
153 |
||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
PGA |
Square |
Ceramic |
35 ns |
No |
128 |
CMOS |
38535Q/M;38534H;883B |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Programmable Logic Devices |
No |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Perpendicular |
S-XPGA-P68 |
No |
No |
||||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
27 ns |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier |
Registered |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Quad |
S-PQCC-J84 |
5.08 mm |
29.3116 mm |
No |
576 Logic elements; Built-in JTAG boundry-scan test circuitry |
53.76 MHz |
29.3116 mm |
|||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
WPGA |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
No |
5.5 V |
CMOS |
5 |
Grid Array, Window |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
7 Dedicated Inputs, 52 I/O |
7 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P68 |
3.81 mm |
27.94 mm |
No |
Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
33.3 MHz |
27.94 mm |
52 |
||||||||||||||||||||
Altera |
EE PLD |
Military |
Pin/Peg |
192 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
15 ns |
No |
2.625 V |
CMOS |
MIL-STD-883 |
2.5 |
Grid Array |
Macrocell |
2.375 V |
2.54 mm |
125 °C (257 °F) |
0 Dedicated Inputs |
0 |
-55 °C (-67 °F) |
Gold |
Perpendicular |
S-CPGA-P192 |
5.43 mm |
45.15 mm |
No |
256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock |
e4 |
76.9 MHz |
220 °C (428 °F) |
45.15 mm |
|||||||||||||||||
Altera |
Loadable PLD |
Military |
Ball |
225 |
BGA |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
1.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 148 I/O |
4 |
-55 °C (-67 °F) |
Tin Silver Copper |
Bottom |
S-PBGA-B225 |
2.3 mm |
27 mm |
No |
820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e1 |
27 mm |
148 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
240 |
HFQFP |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 180 I/O |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G240 |
4.1 mm |
32 mm |
No |
1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e3 |
32 mm |
180 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
J Bend |
44 |
QCCJ |
Square |
Ceramic, Glass-Sealed |
60 ns |
Yes |
5.5 V |
CMOS |
MIL-STD-883 Class B |
36 |
PAL-TYPE |
5 |
5 V |
Chip Carrier |
LDCC44,.7SQ |
Programmable Logic Devices |
Macrocell |
4.5 V |
240 |
1.27 mm |
125 °C (257 °F) |
12 Dedicated Inputs, 24 I/O |
12 |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-GQCC-J44 |
4.57 mm |
16.51 mm |
No |
24 Macrocells |
e0 |
20 MHz |
24 |
220 °C (428 °F) |
16.51 mm |
24 |
|||||||||
Altera |
UV PLD |
Military |
J Bend |
68 |
QCCJ |
Square |
Ceramic |
90 ns |
Yes |
48 |
CMOS |
38535Q/M;38534H;883B |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Programmable Logic Devices |
No |
1.27 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Quad |
S-XQCC-J68 |
No |
No |
||||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
240 |
FQFP |
Square |
Plastic/Epoxy |
23.8 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G240 |
4.1 mm |
32 mm |
No |
1152 Logic elements; Built-in JTAG boundry-scan test circuitry |
e3 |
60.6 MHz |
32 mm |
|||||||||||||||||||
Altera |
UV PLD |
Military |
J Bend |
84 |
WQCCJ |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier, Window |
Macrocell |
4.5 V |
1.27 mm |
125 °C (257 °F) |
19 Dedicated Inputs, 48 I/O |
19 |
-55 °C (-67 °F) |
Quad |
S-CQCC-J84 |
5.08 mm |
29.21 mm |
No |
128 Macrocells; Shared Input/Clock; Shared Product Terms |
33.3 MHz |
29.21 mm |
48 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
240 |
FQFP |
Square |
Plastic/Epoxy |
23.8 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G240 |
4.1 mm |
32 mm |
No |
2304 Logic elements; Built-in JTAG boundry-scan test circuitry |
e3 |
60.6 MHz |
32 mm |
|||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
232 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
MIL-STD-883 |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 180 I/O |
4 |
-55 °C (-67 °F) |
Gold |
Perpendicular |
S-CPGA-P232 |
5.207 mm |
44.7 mm |
No |
1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e4 |
220 °C (428 °F) |
44.7 mm |
180 |
||||||||||||||||||
Altera |
UV PLD |
Military |
J Bend |
44 |
WQCCJ |
Square |
Ceramic, Glass-Sealed |
60 ns |
Yes |
5.5 V |
CMOS |
36 |
PAL-TYPE |
5 |
5 V |
Chip Carrier, Window |
LDCC44,.7SQ |
Programmable Logic Devices |
Macrocell |
4.5 V |
240 |
1.27 mm |
125 °C (257 °F) |
12 Dedicated Inputs, 24 I/O |
12 |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-GQCC-J44 |
4.57 mm |
16.51 mm |
No |
24 Macrocells |
e0 |
20 MHz |
24 |
220 °C (428 °F) |
16.51 mm |
24 |
||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
240 |
FQFP |
Square |
Plastic/Epoxy |
27 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G240 |
4.1 mm |
32 mm |
No |
2304 Logic elements; Built-in JTAG boundry-scan test circuitry |
e3 |
53.76 MHz |
32 mm |
|||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
208 |
FQFP |
Square |
Plastic/Epoxy |
23.8 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G208 |
4.1 mm |
28 mm |
No |
576 Logic elements Configurable I/O operation with 3.3 V or 5 V |
e3 |
60.6 MHz |
28 mm |
|||||||||||||||||||
Altera |
Loadable PLD |
Military |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
27 ns |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier |
Registered |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Quad |
S-PQCC-J84 |
5.08 mm |
29.3116 mm |
No |
1152 Logic elements; Built-in JTAG boundry-scan test circuitry |
53.76 MHz |
29.3116 mm |
|||||||||||||||||||||
Altera |
OT PLD |
Military |
J Bend |
28 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier |
Registered |
4.5 V |
1.27 mm |
125 °C (257 °F) |
8 Dedicated Inputs, 0 I/O |
8 |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-PQCC-J28 |
4.572 mm |
11.5062 mm |
No |
Stand-Alone Microsequencer |
e0 |
20 MHz |
220 °C (428 °F) |
11.5062 mm |
0 |
||||||||||||||||||
Altera |
UV PLD |
Military |
Through-Hole |
24 |
DIP |
Rectangular |
Ceramic, Glass-Sealed |
25 ns |
No |
5.5 V |
CMOS |
MIL-STD-883 |
5 |
In-Line |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
11 Dedicated Inputs, 10 I/O |
11 |
-55 °C (-67 °F) |
Dual |
R-GDIP-T24 |
5.08 mm |
7.62 mm |
No |
30.3 MHz |
32 mm |
10 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
208 |
HFQFP |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G208 |
4.1 mm |
28 mm |
No |
1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e3 |
28 mm |
|||||||||||||||||||||
Altera |
Military |
J Bend |
44 |
QCCJ |
Square |
Ceramic |
Yes |
CMOS |
38535Q/M;38534H;883B |
36 |
PAL-TYPE |
Chip Carrier |
LDCC44,.7SQ |
Programmable Logic Devices |
236 |
1.27 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-XQCC-J44 |
No |
e0 |
12.5 MHz |
24 |
220 °C (428 °F) |
|||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
240 |
HFQFP |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G240 |
4.1 mm |
32 mm |
No |
1500 Flip Flops; 1296 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e3 |
32 mm |
|||||||||||||||||||||
Altera |
Loadable PLD |
Military |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier |
Registered |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 64 I/O |
4 |
-55 °C (-67 °F) |
Quad |
S-PQCC-J84 |
5.08 mm |
29.3116 mm |
No |
282 Flip Flops; 208 Logic elements; Built-in JTAG boundry-scan test circuitry |
29.3116 mm |
64 |
||||||||||||||||||||||
Altera |
Military |
Through-Hole |
28 |
DIP |
Rectangular |
Plastic/Epoxy |
25 ns |
No |
CMOS |
24 |
PAL-TYPE |
5 |
5 V |
In-Line |
DIP28,.3 |
Programmable Logic Devices |
320 |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Dual |
R-PDIP-T28 |
No |
e0 |
62.5 MHz |
16 |
220 °C (428 °F) |
|||||||||||||||||||||
Altera |
OT PLD |
Military |
J Bend |
28 |
QCCJ |
Square |
Plastic/Epoxy |
12 ns |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier |
Macrocell |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 16 I/O |
4 |
-55 °C (-67 °F) |
Quad |
S-PQCC-J28 |
4.572 mm |
11.5062 mm |
No |
Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks |
83.3 MHz |
11.5062 mm |
16 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
J Bend |
44 |
WQCCJ |
Square |
Ceramic, Glass-Sealed |
90 ns |
Yes |
5.5 V |
CMOS |
36 |
PAL-TYPE |
5 |
Chip Carrier, Window |
LDCC44,.7SQ |
Programmable Logic Devices |
Macrocell |
4.5 V |
236 |
1.27 mm |
125 °C (257 °F) |
12 Dedicated Inputs, 24 I/O |
12 |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-GQCC-J44 |
4.57 mm |
16.51 mm |
No |
28 Macrocells |
e0 |
17.5 MHz |
24 |
220 °C (428 °F) |
16.51 mm |
24 |
|||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
208 |
FQFP |
Square |
Plastic/Epoxy |
27 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G208 |
4.1 mm |
28 mm |
No |
576 Logic elements Configurable I/O operation with 3.3 V or 5 V |
e3 |
53.76 MHz |
28 mm |
|||||||||||||||||||
Altera |
Military |
J Bend |
28 |
QCCJ |
Square |
Plastic/Epoxy |
25 ns |
Yes |
CMOS |
24 |
PAL-TYPE |
5 |
5 V |
Chip Carrier |
LDCC28,.5SQ |
Programmable Logic Devices |
320 |
1.27 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-PQCC-J28 |
No |
e0 |
62.5 MHz |
16 |
220 °C (428 °F) |
|||||||||||||||||||||
Altera |
OT PLD |
Military |
Gull Wing |
24 |
SOP |
Rectangular |
Plastic/Epoxy |
12 ns |
Yes |
5.5 V |
CMOS |
5 |
Small Outline |
Macrocell |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 16 I/O |
4 |
-55 °C (-67 °F) |
Dual |
R-PDSO-G24 |
2.65 mm |
7.5 mm |
No |
Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks |
83.3 MHz |
15.4 mm |
16 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
PGA |
Square |
85 ns |
No |
5.5 V |
CMOS |
MIL-STD-883 |
5 |
Grid Array |
Macrocell |
4.5 V |
125 °C (257 °F) |
11 Dedicated Inputs, 48 I/O |
11 |
-55 °C (-67 °F) |
Perpendicular |
S-XPGA-P68 |
No |
12.2 MHz |
48 |
|||||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
160 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 116 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P160 |
5.34 mm |
39.624 mm |
No |
452 Flip Flops; 336 Logic Elements |
39.624 mm |
116 |
||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier |
Registered |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 64 I/O |
4 |
-55 °C (-67 °F) |
Quad |
S-PQCC-J84 |
5.08 mm |
29.3116 mm |
No |
452 Flip Flops; 336 Logic Elements |
29.3116 mm |
64 |
||||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
100 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
59 ns |
No |
5.5 V |
CMOS |
MIL-STD-883 Class B |
5 |
Grid Array |
Macrocell |
4.5 V |
125 °C (257 °F) |
19 Dedicated Inputs, 64 I/O |
19 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P100 |
No |
27.7 MHz |
64 |
||||||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
WPGA |
Square |
Ceramic, Metal-Sealed Cofired |
50 ns |
No |
5.5 V |
CMOS |
5 |
Grid Array, Window |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
12 Dedicated Inputs, 48 I/O |
12 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P68 |
4.953 mm |
27.94 mm |
No |
48 Macrocells; Shared Input/Clock |
22.2 MHz |
27.94 mm |
48 |
||||||||||||||||||||
Altera |
Military |
Through-Hole |
20 |
DIP |
Rectangular |
Ceramic |
50 ns |
No |
CMOS |
38535Q/M;38534H;883B |
18 |
PAL-TYPE |
5 |
5 V |
In-Line |
DIP20,.3 |
Programmable Logic Devices |
Macrocell |
74 |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Dual |
R-XDIP-T20 |
No |
16.6 MHz |
8 |
||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
160 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 116 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P160 |
5.34 mm |
39.624 mm |
No |
Labs With Fasttrack Interconnect; 452 Flip Flops; 336 Logic Elements |
39.624 mm |
116 |
||||||||||||||||||||||
Altera |
EE PLD |
Military |
Pin/Peg |
280 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
12 ns |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
0 Dedicated Inputs, 184 I/O |
0 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P280 |
5.081 mm |
49.78 mm |
No |
400 Macrocells; 580 Flip Flops; Configurable I/O operation with 3.3 V or 5 V |
118 MHz |
49.78 mm |
184 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
280 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 204 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P280 |
5.081 mm |
49.78 mm |
No |
1500 Flip Flops; 1296 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
49.78 mm |
204 |
||||||||||||||||||||||
Altera |
UV PLD |
Military |
Through-Hole |
24 |
DIP |
Rectangular |
Ceramic, Glass-Sealed |
No |
CMOS |
In-Line |
Macrocell |
125 °C (257 °F) |
11 Dedicated Inputs, 10 I/O |
11 |
-55 °C (-67 °F) |
Dual |
R-GDIP-T24 |
No |
10 |
||||||||||||||||||||||||||||||
Altera |
EE PLD |
Military |
Gull Wing |
208 |
HFQFP |
Square |
Plastic/Epoxy |
20 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug, Fine Pitch |
Macrocell |
4.5 V |
.5 mm |
125 °C (257 °F) |
0 Dedicated Inputs, 153 I/O |
0 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G208 |
4.1 mm |
28 mm |
No |
560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V |
e3 |
95.2 MHz |
28 mm |
153 |
||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
504 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
23.8 ns |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
125 °C (257 °F) |
4 Dedicated Inputs, 406 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P504 |
No |
4992 Logic elements Configurable I/O operation with 3.3 V or 5 V |
60.6 MHz |
406 |
||||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Flatpack |
Registered |
4.5 V |
.65 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 116 I/O |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G160 |
4.07 mm |
28 mm |
No |
452 Flip Flops; 336 Logic Elements |
e3 |
28 mm |
116 |
Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.
PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.
PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.