Part | RoHS | Manufacturer | Programmable IC Type | Grading Of Temperature | Form Of Terminal | No. of Terminals | Package Code | Package Shape | Package Body Material | Propagation Delay | No. of Logic Cells | Surface Mount | Maximum Supply Voltage | No. of Macro Cells | Technology Used | Screening Level | No. of Inputs | Architecture | Nominal Supply Voltage (V) | Packing Method | Power Supplies (V) | Package Style (Meter) | Package Equivalence Code | Sub-Category | In-System Programmable | Output Function | Minimum Supply Voltage | No. of Product Terms | Pitch Of Terminal | Maximum Operating Temperature | Organization | No. of Dedicated Inputs | Minimum Operating Temperature | Finishing Of Terminal Used | Position Of Terminal | JESD-30 Code | Moisture Sensitivity Level (MSL) | Maximum Seated Height | Width | Qualification | Additional Features | JESD-609 Code | Maximum Clock Frequency | Maximum Time At Peak Reflow Temperature (s) | No. of Outputs | Peak Reflow Temperature (C) | Length | JTAG Boundary Scan Test | No. of I/O Lines |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Altera |
Military |
Through-Hole |
20 |
DIP |
Rectangular |
Ceramic |
50 ns |
No |
CMOS |
38535Q/M;38534H;883B |
18 |
PAL-TYPE |
5 |
5 V |
In-Line |
DIP20,.3 |
Programmable Logic Devices |
Macrocell |
74 |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Dual |
R-XDIP-T20 |
No |
16.6 MHz |
8 |
||||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
100 |
WPGA |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
No |
5.5 V |
128 |
CMOS |
38535Q/M;38534H;883B |
5 |
5 V |
Grid Array, Window |
PGA100M,13X13 |
Programmable Logic Devices |
No |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
19 Dedicated Inputs, 64 I/O |
19 |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-CPGA-P100 |
3.81 mm |
33.528 mm |
No |
Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
e0 |
33.3 MHz |
220 °C (428 °F) |
33.528 mm |
No |
64 |
||||||||||
Altera |
UV PLD |
Military |
Gull Wing |
100 |
WQFP |
Rectangular |
Ceramic, Metal-Sealed Cofired |
45 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Window |
Macrocell |
4.5 V |
.65 mm |
125 °C (257 °F) |
19 Dedicated Inputs, 64 I/O |
19 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
R-CQFP-G100 |
2.99 mm |
14 mm |
No |
Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
e3 |
40 MHz |
19.2 mm |
64 |
||||||||||||||||||
Altera |
Military |
Through-Hole |
24 |
DIP |
Rectangular |
Ceramic |
No |
CMOS |
20 |
PAL-TYPE |
5 |
5 V |
In-Line |
DIP24,.3 |
Programmable Logic Devices |
Macrocell |
160 |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Dual |
R-XDIP-T24 |
No |
18.2 MHz |
16 |
||||||||||||||||||||||||
Altera |
Military |
J Bend |
28 |
QCCJ |
Square |
Ceramic |
Yes |
CMOS |
20 |
PAL-TYPE |
5 |
5 V |
Chip Carrier |
LDCC28,.5SQ |
Programmable Logic Devices |
Macrocell |
160 |
1.27 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-XQCC-J28 |
No |
e0 |
25 MHz |
16 |
220 °C (428 °F) |
|||||||||||||||||||||
Altera |
UV PLD |
Military |
Through-Hole |
24 |
WDIP |
Rectangular |
Ceramic, Glass-Sealed |
15 ns |
No |
5.5 V |
CMOS |
5 |
In-Line, Window |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
11 Dedicated Inputs, 10 I/O |
11 |
-55 °C (-67 °F) |
Dual |
R-GDIP-T24 |
5.08 mm |
7.62 mm |
No |
10 Macrocells; 1 External Clock; Shared Input/Clock; Variable Product Terms |
50 MHz |
32 mm |
10 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
PGA |
Square |
Ceramic |
90 ns |
No |
48 |
CMOS |
38535Q/M;38534H;883B |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Programmable Logic Devices |
No |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-XPGA-P68 |
No |
e0 |
220 °C (428 °F) |
No |
|||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
160 |
HQFP |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug |
Registered |
4.5 V |
.65 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G160 |
3.91 mm |
28 mm |
No |
820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e3 |
28 mm |
|||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
160 |
HQFP |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug |
Registered |
4.5 V |
.65 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G160 |
3.91 mm |
28 mm |
No |
636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e3 |
28 mm |
|||||||||||||||||||||
Altera |
Military |
Through-Hole |
40 |
DIP |
Rectangular |
Ceramic |
60 ns |
No |
CMOS |
38535Q/M;38534H;883B |
36 |
PAL-TYPE |
5 |
5 V |
In-Line |
DIP40,.6 |
Programmable Logic Devices |
Macrocell |
240 |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Dual |
R-XDIP-T40 |
No |
16.7 MHz |
24 |
||||||||||||||||||||||
Altera |
EE PLD |
Military |
Gull Wing |
240 |
HFQFP |
Square |
Plastic/Epoxy |
15 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug, Fine Pitch |
Macrocell |
4.5 V |
.5 mm |
125 °C (257 °F) |
0 Dedicated Inputs, 191 I/O |
0 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G240 |
4.1 mm |
32 mm |
No |
560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V |
e3 |
117.6 MHz |
32 mm |
191 |
||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
208 |
FQFP |
Square |
Plastic/Epoxy |
27 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G208 |
4.1 mm |
28 mm |
No |
1152 Logic elements Configurable I/O operation with 3.3 V or 5 V |
e3 |
53.76 MHz |
28 mm |
|||||||||||||||||||
Altera |
Loadable PLD |
Military |
Ball |
560 |
BGA |
Square |
Plastic/Epoxy |
23.8 ns |
Yes |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Tin Silver Copper |
Bottom |
S-PBGA-B560 |
No |
4992 Logic elements Configurable I/O operation with 3.3 V or 5 V |
e1 |
60.6 MHz |
|||||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
WPGA |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
No |
128 |
CMOS |
38535Q/M;38534H;883B |
5 |
5 V |
Grid Array, Window |
PGA68,11X11 |
Programmable Logic Devices |
No |
Macrocell |
2.54 mm |
125 °C (257 °F) |
7 Dedicated Inputs, 52 I/O |
7 |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-CPGA-P68 |
4.96 mm |
27.94 mm |
No |
Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
e0 |
33.3 MHz |
220 °C (428 °F) |
27.94 mm |
No |
52 |
||||||||||||
Altera |
EE PLD |
Military |
Pin/Peg |
192 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
20 ns |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
0 Dedicated Inputs, 160 I/O |
0 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P192 |
5.43 mm |
45.15 mm |
No |
256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock |
62.5 MHz |
45.15 mm |
160 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
403 |
IPGA |
Square |
Ceramic, Metal-Sealed Cofired |
23.8 ns |
No |
5.5 V |
CMOS |
5 |
Grid Array, Interstitial Pitch |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 248 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P403 |
3.916 mm |
49.78 mm |
No |
1728 Logic elements Configurable I/O operation with 3.3 V or 5 V |
60.6 MHz |
49.78 mm |
248 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
84 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
90 ns |
No |
5.5 V |
192 |
CMOS |
MIL-STD-883 Class B |
5 |
5 V |
Grid Array |
PGA84M,11X11 |
Programmable Logic Devices |
No |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
7 Dedicated Inputs, 64 I/O |
7 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P84 |
4.96 mm |
28.45 mm |
No |
19.6 MHz |
220 °C (428 °F) |
28.45 mm |
No |
64 |
|||||||||||||
Altera |
Loadable PLD |
Military |
Ball |
356 |
HLBGA |
Square |
Plastic/Epoxy |
27 ns |
Yes |
5.5 V |
CMOS |
5 |
Grid Array, Heat Sink/Slug, Low Profile |
Registered |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Tin Silver Copper |
Bottom |
S-PBGA-B356 |
1.63 mm |
35 mm |
No |
1152 Logic elements Configurable I/O operation with 3.3 V or 5 V |
e1 |
53.76 MHz |
35 mm |
|||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
240 |
HFQFP |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Heat Sink/Slug, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 180 I/O |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G240 |
4.1 mm |
32 mm |
No |
1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e3 |
32 mm |
180 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
232 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 180 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P232 |
5.207 mm |
44.7 mm |
No |
1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
44.7 mm |
180 |
||||||||||||||||||||||
Altera |
EE PLD |
Military |
Through-Hole |
20 |
DIP |
Rectangular |
Ceramic |
45 ns |
No |
CMOS |
18 |
PAL-TYPE |
5 |
5 V |
In-Line |
DIP20,.3 |
Programmable Logic Devices |
Macrocell |
72 |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Dual |
R-XDIP-T20 |
No |
20 MHz |
8 |
||||||||||||||||||||||
Altera |
UV PLD |
Military |
Through-Hole |
40 |
WDIP |
Rectangular |
Ceramic, Glass-Sealed |
65 ns |
No |
5.5 V |
CMOS |
5 |
In-Line, Window |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
12 Dedicated Inputs, 24 I/O |
12 |
-55 °C (-67 °F) |
Dual |
R-GDIP-T40 |
5.715 mm |
15.24 mm |
No |
28 Macrocells |
23.2 MHz |
52.07 mm |
24 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
84 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
59 ns |
No |
5.5 V |
CMOS |
MIL-STD-883 Class B |
5 |
Grid Array |
Macrocell |
4.5 V |
125 °C (257 °F) |
7 Dedicated Inputs, 64 I/O |
7 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P84 |
No |
27.7 MHz |
64 |
||||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
192 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 132 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P192 |
5.43 mm |
45.15 mm |
No |
636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
45.15 mm |
132 |
||||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Ball |
225 |
BGA |
Square |
Plastic/Epoxy |
Yes |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
1.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 148 I/O |
4 |
-55 °C (-67 °F) |
Tin Silver Copper |
Bottom |
S-PBGA-B225 |
2.3 mm |
27 mm |
No |
820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
e1 |
27 mm |
148 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
100 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
59 ns |
No |
5.5 V |
128 |
CMOS |
MIL-STD-883 Class B |
5 |
5 V |
Grid Array |
PGA100M,13X13 |
Programmable Logic Devices |
No |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
19 Dedicated Inputs, 64 I/O |
19 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P100 |
No |
27.7 MHz |
220 °C (428 °F) |
No |
64 |
||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
WPGA |
Square |
Ceramic, Metal-Sealed Cofired |
33 ns |
No |
5.5 V |
CMOS |
5 |
Grid Array, Window |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
7 Dedicated Inputs, 52 I/O |
7 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P68 |
3.81 mm |
27.94 mm |
No |
Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
66.7 MHz |
27.94 mm |
52 |
||||||||||||||||||||
Altera |
EE PLD |
Military |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
15 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack |
Macrocell |
4.5 V |
.65 mm |
125 °C (257 °F) |
0 Dedicated Inputs, 120 I/O |
0 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G160 |
4.07 mm |
28 mm |
No |
192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock |
e3 |
76.9 MHz |
28 mm |
120 |
||||||||||||||||||
Altera |
UV PLD |
Military |
Through-Hole |
40 |
WDIP |
Rectangular |
Ceramic, Glass-Sealed |
90 ns |
No |
5.5 V |
CMOS |
36 |
PAL-TYPE |
5 |
In-Line, Window |
DIP40,.6 |
Programmable Logic Devices |
Macrocell |
4.5 V |
236 |
2.54 mm |
125 °C (257 °F) |
12 Dedicated Inputs, 24 I/O |
12 |
-55 °C (-67 °F) |
Tin Lead |
Dual |
R-GDIP-T40 |
5.715 mm |
15.24 mm |
No |
28 Macrocells |
e0 |
17.5 MHz |
24 |
220 °C (428 °F) |
52.07 mm |
24 |
|||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
240 |
FQFP |
Square |
Plastic/Epoxy |
23.8 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 189 I/O |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G240 |
4.1 mm |
32 mm |
No |
2880 Logic elements; Built-in JTAG boundry-scan test circuitry |
e3 |
60.6 MHz |
32 mm |
189 |
||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
PGA |
Square |
Ceramic |
90 ns |
No |
48 |
CMOS |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Programmable Logic Devices |
No |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Perpendicular |
S-XPGA-P68 |
No |
No |
|||||||||||||||||||||||||
Altera |
EE PLD |
Military |
Gull Wing |
208 |
FQFP |
Square |
Ceramic, Metal-Sealed Cofired |
15 ns |
Yes |
2.625 V |
CMOS |
MIL-STD-883 |
2.5 |
Flatpack, Fine Pitch |
Macrocell |
2.375 V |
.5 mm |
125 °C (257 °F) |
0 Dedicated Inputs |
0 |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-CQFP-G208 |
3.82 mm |
27.2 mm |
No |
256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock |
e0 |
76.9 MHz |
27.2 mm |
||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
PGA |
Square |
Ceramic |
75 ns |
No |
48 |
CMOS |
38535Q/M;38534H;883B |
5 |
5 V |
Grid Array |
PGA68,11X11 |
Programmable Logic Devices |
No |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Perpendicular |
S-XPGA-P68 |
No |
e0 |
220 °C (428 °F) |
No |
|||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Pin/Peg |
232 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.5 V |
CMOS |
5 |
Grid Array |
Registered |
4.5 V |
2.54 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 180 I/O |
4 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P232 |
5.207 mm |
44.7 mm |
No |
1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V |
44.7 mm |
180 |
||||||||||||||||||||||
Altera |
Military |
Through-Hole |
20 |
DIP |
Rectangular |
Ceramic |
No |
CMOS |
18 |
PAL-TYPE |
5 |
5 V |
In-Line |
DIP20,.3 |
Programmable Logic Devices |
Macrocell |
74 |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Dual |
R-XDIP-T20 |
No |
23.8 MHz |
8 |
||||||||||||||||||||||||
Altera |
UV PLD |
Military |
J Bend |
68 |
WQCCJ |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
Yes |
128 |
CMOS |
5 |
5 V |
Chip Carrier, Window |
LDCC68,1.0SQ |
Programmable Logic Devices |
No |
Macrocell |
1.27 mm |
125 °C (257 °F) |
7 Dedicated Inputs, 52 I/O |
7 |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-CQCC-J68 |
5.08 mm |
24.13 mm |
No |
Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
e0 |
33.3 MHz |
220 °C (428 °F) |
24.13 mm |
No |
52 |
|||||||||||||
Altera |
UV PLD |
Military |
J Bend |
68 |
WQCCJ |
Square |
Ceramic, Metal-Sealed Cofired |
50 ns |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier, Window |
Macrocell |
4.5 V |
1.27 mm |
125 °C (257 °F) |
12 Dedicated Inputs, 48 I/O |
12 |
-55 °C (-67 °F) |
Quad |
S-CQCC-J68 |
4.826 mm |
24.13 mm |
No |
48 Macrocells; 4 External Clocks; Shared Input/Clock |
22.2 MHz |
24.13 mm |
48 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
208 |
FQFP |
Square |
Plastic/Epoxy |
27 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G208 |
4.1 mm |
28 mm |
No |
1728 Logic elements Configurable I/O operation with 3.3 V or 5 V |
e3 |
53.76 MHz |
28 mm |
|||||||||||||||||||
Altera |
OT PLD |
Military |
J Bend |
28 |
QCCJ |
Square |
Plastic/Epoxy |
10 ns |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier |
Macrocell |
4.5 V |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 16 I/O |
4 |
-55 °C (-67 °F) |
Quad |
S-PQCC-J28 |
4.572 mm |
11.5062 mm |
No |
Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks |
100 MHz |
11.5062 mm |
16 |
||||||||||||||||||||
Altera |
Loadable PLD |
Military |
Gull Wing |
208 |
FQFP |
Square |
Plastic/Epoxy |
23.8 ns |
Yes |
5.5 V |
CMOS |
5 |
Flatpack, Fine Pitch |
Registered |
4.5 V |
.5 mm |
125 °C (257 °F) |
4 Dedicated Inputs |
4 |
-55 °C (-67 °F) |
Matte Tin |
Quad |
S-PQFP-G208 |
4.1 mm |
28 mm |
No |
1728 Logic elements Configurable I/O operation with 3.3 V or 5 V |
e3 |
60.6 MHz |
28 mm |
|||||||||||||||||||
Altera |
UV PLD |
Military |
Through-Hole |
24 |
WDIP |
Rectangular |
Ceramic, Metal-Sealed Cofired |
55 ns |
No |
5.5 V |
MIL-STD-883 Class B |
5 |
In-Line, Window |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Dual |
R-CDIP-T24 |
4.826 mm |
7.62 mm |
No |
e0 |
23.3 MHz |
220 °C (428 °F) |
31.9405 mm |
|||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
100 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
75 ns |
No |
5.5 V |
CMOS |
MIL-STD-883 Class B |
5 |
Grid Array |
Macrocell |
4.5 V |
125 °C (257 °F) |
19 Dedicated Inputs, 64 I/O |
19 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P100 |
No |
22.2 MHz |
64 |
||||||||||||||||||||||||
Altera |
UV PLD |
Military |
J Bend |
68 |
WQCCJ |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier, Window |
Macrocell |
4.5 V |
1.27 mm |
125 °C (257 °F) |
7 Dedicated Inputs, 52 I/O |
7 |
-55 °C (-67 °F) |
Quad |
S-CQCC-J68 |
4.826 mm |
24.13 mm |
No |
Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
33.3 MHz |
24.13 mm |
52 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
Pin/Peg |
68 |
WPGA |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
No |
5.5 V |
CMOS |
5 |
Grid Array, Window |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
7 Dedicated Inputs, 52 I/O |
7 |
-55 °C (-67 °F) |
Perpendicular |
S-CPGA-P68 |
4.953 mm |
27.94 mm |
No |
128 Macrocells; Shared Input/Clock; Shared Product Terms |
33.3 MHz |
27.94 mm |
52 |
||||||||||||||||||||
Altera |
Military |
J Bend |
28 |
QCCJ |
Square |
Ceramic |
22 ns |
Yes |
CMOS |
20 |
PAL-TYPE |
5 |
5 V |
Chip Carrier |
LDCC28,.5SQ |
Programmable Logic Devices |
Macrocell |
160 |
1.27 mm |
125 °C (257 °F) |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-XQCC-J28 |
No |
e0 |
55.5 MHz |
16 |
220 °C (428 °F) |
||||||||||||||||||||
Altera |
UV PLD |
Military |
J Bend |
84 |
WQCCJ |
Square |
Ceramic, Metal-Sealed Cofired |
45 ns |
Yes |
5.5 V |
CMOS |
5 |
Chip Carrier, Window |
Macrocell |
4.5 V |
1.27 mm |
125 °C (257 °F) |
19 Dedicated Inputs, 48 I/O |
19 |
-55 °C (-67 °F) |
Quad |
S-CQCC-J84 |
5.08 mm |
29.21 mm |
No |
Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock |
40 MHz |
29.21 mm |
48 |
||||||||||||||||||||
Altera |
UV PLD |
Military |
Through-Hole |
24 |
WDIP |
Rectangular |
Ceramic, Glass-Sealed |
10 ns |
No |
5.5 V |
CMOS |
5 |
In-Line, Window |
Macrocell |
4.5 V |
2.54 mm |
125 °C (257 °F) |
11 Dedicated Inputs, 10 I/O |
11 |
-55 °C (-67 °F) |
Tin Lead |
Dual |
R-GDIP-T24 |
5.08 mm |
7.62 mm |
No |
10 Macrocells; 1 External Clock; Shared Input/Clock; Variable Product Terms |
e0 |
83 MHz |
32 mm |
10 |
||||||||||||||||||
Altera |
UV PLD |
Military |
J Bend |
28 |
WQCCJ |
Square |
Ceramic, Metal-Sealed Cofired |
55 ns |
Yes |
5.5 V |
CMOS |
20 |
PAL-TYPE |
5 |
5 V |
Chip Carrier, Window |
LDCC28,.5SQ |
Programmable Logic Devices |
Macrocell |
4.5 V |
160 |
1.27 mm |
125 °C (257 °F) |
4 Dedicated Inputs, 16 I/O |
4 |
-55 °C (-67 °F) |
Tin Lead |
Quad |
S-CQCC-J28 |
4.57 mm |
11.43 mm |
No |
16 Macrocells |
e0 |
22.2 MHz |
16 |
220 °C (428 °F) |
11.43 mm |
16 |
Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.
PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.
PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.