Military Programmable Logic Devices (PLD) 1,614

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	No. of Inputs	Architecture	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	No. of Product Terms	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EP630JM-20	Altera		Military	J Bend	28	QCCJ	Square	Ceramic	22 ns	Yes			CMOS		20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell		160	1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-XQCC-J28				No		e0	55.5 MHz	16	220 °C (428 °F)
EPM5130JM-2	Altera	UV PLD	Military	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	45 ns	Yes	5.5 V		CMOS				5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	19 Dedicated Inputs, 48 I/O	19	-55 °C (-67 °F)		Quad	S-CQCC-J84		5.08 mm	29.21 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz			29.21 mm		48
5962-8753906LX	Altera	UV PLD	Military	Through-Hole	24	WDIP	Rectangular	Ceramic, Glass-Sealed	10 ns	No	5.5 V		CMOS				5		In-Line, Window				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	11 Dedicated Inputs, 10 I/O	11	-55 °C (-67 °F)	Tin Lead	Dual	R-GDIP-T24		5.08 mm	7.62 mm	No	10 Macrocells; 1 External Clock; Shared Input/Clock; Variable Product Terms	e0	83 MHz			32 mm		10
EP600JMB	Altera	UV PLD	Military	J Bend	28	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns	Yes	5.5 V		CMOS		20	PAL-TYPE	5	5 V	Chip Carrier, Window	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.5 V	160	1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J28		4.57 mm	11.43 mm	No	16 Macrocells	e0	22.2 MHz	16	220 °C (428 °F)	11.43 mm		16
EPF10K70QM240-4	Altera	Loadable PLD	Military	Gull Wing	240	FQFP	Square	Plastic/Epoxy	23.8 ns	Yes	5.5 V		CMOS				5		Flatpack, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G240		4.1 mm	32 mm	No	3744 Logic elements; Built-in JTAG boundry-scan test circuitry	e3	60.6 MHz			32 mm
EPM9320LM84-12	Altera	EE PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	12 ns	Yes	5.5 V		CMOS				5		Chip Carrier				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	0 Dedicated Inputs, 55 I/O	0	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	320 Macrocells; 484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz			29.3116 mm		55
EPF81188ARM208-6	Altera	Loadable PLD	Military	Gull Wing	208	HFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G208		4.1 mm	28 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e3				28 mm
EPM9480GM280-15	Altera	EE PLD	Military	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns	No	5.5 V		CMOS				5		Grid Array				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 200 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	480 Macrocells; 676 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz			49.78 mm		200
EP600DM883B	Altera		Military	Through-Hole	24	DIP	Rectangular	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS	MIL-STD-883 Class B	20	PAL-TYPE	5	5 V	In-Line	DIP24,.3	Programmable Logic Devices		Macrocell	4.5 V	160	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)	Tin Lead	Dual	R-CDIP-T24				No	16 Macrocells	e0	23.3 MHz	16	220 °C (428 °F)			16
EPM9400LM84-12	Altera	EE PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	12 ns	Yes	5.5 V		CMOS				5		Chip Carrier				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	0 Dedicated Inputs, 59 I/O	0	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	400 Macrocells; 580 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz			29.3116 mm		59
EPM9560RM304-15	Altera	EE PLD	Military	Gull Wing	304	HFQFP	Square	Plastic/Epoxy	15 ns	Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Macrocell	4.5 V		.5 mm	125 °C (257 °F)	0 Dedicated Inputs, 216 I/O	0	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G304		4.5 mm	40 mm	No	560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V	e3	117.6 MHz			40 mm		216
EPF10K20LM84-4	Altera	Loadable PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	23.8 ns	Yes	5.5 V		CMOS				5		Chip Carrier				Registered	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	1152 Logic elements; Built-in JTAG boundry-scan test circuitry		60.6 MHz			29.3116 mm
EPF81188RM208-3	Altera	Loadable PLD	Military	Gull Wing	208	HFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G208		4.1 mm	28 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e3				28 mm
EPF8636ALM84-5	Altera	Loadable PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Chip Carrier				Registered	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 64 I/O	4	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V					29.3116 mm		64
5962-01-343-0218	Altera	UV PLD	Military	J Bend	68	QCCJ	Square	Ceramic	90 ns	Yes		48	CMOS				5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No				1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-XQCC-J68	1			No		e0					No
EPF10K30QM240-4	Altera	Loadable PLD	Military	Gull Wing	240	FQFP	Square	Plastic/Epoxy	23.8 ns	Yes	5.5 V		CMOS				5		Flatpack, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G240		4.1 mm	32 mm	No	1728 Logic elements; Built-in JTAG boundry-scan test circuitry	e3	60.6 MHz			32 mm
EP320DM	Altera	UV PLD	Military	Through-Hole	20	WDIP	Rectangular	Ceramic, Glass-Sealed	45 ns	No	5.5 V		CMOS		18	PAL-TYPE	5	5 V	In-Line, Window	DIP20,.3	Programmable Logic Devices		Macrocell	4.5 V	72	2.54 mm	125 °C (257 °F)	9 Dedicated Inputs, 8 I/O	9	-55 °C (-67 °F)	Tin Lead	Dual	R-GDIP-T20		4.826 mm	7.62 mm	No	8 Macrocells; Shared Input/Clock	e0	30.3 MHz	8	220 °C (428 °F)	24.003 mm		8
EPF8452QM160-2	Altera	Loadable PLD	Military	Gull Wing	160	QFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack				Registered	4.5 V		.65 mm	125 °C (257 °F)	4 Dedicated Inputs, 116 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G160		4.07 mm	28 mm	No	Labs With Fasttrack Interconnect; 452 Flip Flops; 336 Logic Elements	e3				28 mm		116
EPF8282VTM100-4	Altera	Loadable PLD	Military	Gull Wing	100	LFQFP	Square	Plastic/Epoxy		Yes			CMOS				3.3		Flatpack, Low Profile, Fine Pitch				Registered			.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 74 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G100		1.27 mm	14 mm	No	282 Flip Flops; 208 Logic elements; Built-in JTAG boundry-scan test circuitry	e3				14 mm		74
EPM5192GM84	Altera	UV PLD	Military	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS				5		Grid Array, Window				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		4.96 mm	27.94 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz			27.94 mm		64
EPF8282VTM100-3	Altera	Loadable PLD	Military	Gull Wing	100	LFQFP	Square	Plastic/Epoxy		Yes			CMOS				3.3		Flatpack, Low Profile, Fine Pitch				Registered			.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 74 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G100		1.27 mm	14 mm	No	282 Flip Flops; 208 Logic elements; Built-in JTAG boundry-scan test circuitry	e3				14 mm		74
EPM9560GM280-20	Altera	EE PLD	Military	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns	No	5.5 V		CMOS				5		Grid Array				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 216 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		95.2 MHz			49.78 mm		216
EPM5128AGM68-12	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	20 ns	No	5.5 V		CMOS				5		Grid Array, Window				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz			27.94 mm		52
EPM5192AJM84-20	Altera	UV PLD	Military	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns	Yes	5.5 V	192	CMOS				5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J84		5.08 mm	29.21 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock	e0	66.7 MHz		220 °C (428 °F)	29.21 mm	No	64
EPM5128AJM-20	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns	Yes	5.5 V		CMOS				5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		66.7 MHz			24.13 mm		52
EPM5130WM100	Altera	UV PLD	Military	Gull Wing	100	WQFP	Rectangular	Ceramic, Metal-Sealed Cofired	55 ns	Yes	5.5 V		CMOS				5		Flatpack, Window				Macrocell	4.5 V		.65 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)	Matte Tin	Quad	R-CQFP-G100		3.35 mm	13.2 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e3	33.3 MHz			19.2 mm		64
EP1800GM	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	90 ns	No		48	CMOS				5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No				2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Perpendicular	S-XPGA-P68				No		e0			220 °C (428 °F)		No
EPM5130QM	Altera	OT PLD	Military	Gull Wing	100	QFP	Rectangular	Plastic/Epoxy	55 ns	Yes	5.5 V	128	CMOS				5	5 V	Flatpack	QFP100,.7X.9	Programmable Logic Devices	No	Macrocell	4.5 V		.65 mm	125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)	Tin Lead	Quad	R-PQFP-G100		3.65 mm	14 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz		220 °C (428 °F)	20 mm	No	64
EPF8820GM883B192-3	Altera	Loadable PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired		No	5.5 V		CMOS				5		Grid Array				Registered	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 148 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V					45.15 mm		148
EP610PM24-35	Altera	OT PLD	Military	Through-Hole	24	DIP	Rectangular	Plastic/Epoxy	37 ns	No	5.5 V		CMOS				5		In-Line				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)		Dual	R-PDIP-T24		4.318 mm	7.62 mm	No	16 Macrocells; 2 External Clocks		28.6 MHz			31.6865 mm		16
EPF8282TM100-2	Altera	Loadable PLD	Military	Gull Wing	100	LFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Low Profile, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 74 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G100		1.27 mm	14 mm	No	282 Flip Flops; 208 Logic elements; Built-in JTAG boundry-scan test circuitry	e3				14 mm		74
5962-9314401MYC	Altera	UV PLD	Military	Pin/Peg	100	PGA	Square	Ceramic, Metal-Sealed Cofired	75 ns	No	5.5 V		CMOS	MIL-STD-883 Class B			5		Grid Array				Macrocell	4.5 V			125 °C (257 °F)	19 Dedicated Inputs, 64 I/O	19	-55 °C (-67 °F)		Perpendicular	S-CPGA-P100				No			22.2 MHz					64
EPF81188RM240-3	Altera	Loadable PLD	Military	Gull Wing	240	HFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 180 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G240		4.1 mm	32 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e3				32 mm		180
EPM9560RM208-25	Altera	EE PLD	Military	Gull Wing	208	HFQFP	Square	Plastic/Epoxy	25 ns	Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Macrocell	4.5 V		.5 mm	125 °C (257 °F)	0 Dedicated Inputs, 153 I/O	0	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G208		4.1 mm	28 mm	No	560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V	e3	66.7 MHz			28 mm		153
5962-01-407-9563	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	35 ns	No		128	CMOS	38535Q/M;38534H;883B			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No				2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)		Perpendicular	S-XPGA-P68				No							No
EPF10K10LM84-5	Altera	Loadable PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	27 ns	Yes	5.5 V		CMOS				5		Chip Carrier				Registered	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	576 Logic elements; Built-in JTAG boundry-scan test circuitry		53.76 MHz			29.3116 mm
EPM5128G5962	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V		CMOS				5		Grid Array, Window				Macrocell	4.5 V		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz			27.94 mm		52
5962-9324702MXC	Altera	EE PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns	No	2.625 V		CMOS	MIL-STD-883			2.5		Grid Array				Macrocell	2.375 V		2.54 mm	125 °C (257 °F)	0 Dedicated Inputs	0	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock	e4	76.9 MHz		220 °C (428 °F)	45.15 mm
EPF8820BM225-3	Altera	Loadable PLD	Military	Ball	225	BGA	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Grid Array				Registered	4.5 V		1.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 148 I/O	4	-55 °C (-67 °F)	Tin Silver Copper	Bottom	S-PBGA-B225		2.3 mm	27 mm	No	820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e1				27 mm		148
EPF81188ARM240-6	Altera	Loadable PLD	Military	Gull Wing	240	HFQFP	Square	Plastic/Epoxy		Yes	5.5 V		CMOS				5		Flatpack, Heat Sink/Slug, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs, 180 I/O	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G240		4.1 mm	32 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e3				32 mm		180
EP900JM883B	Altera	UV PLD	Military	J Bend	44	QCCJ	Square	Ceramic, Glass-Sealed	60 ns	Yes	5.5 V		CMOS	MIL-STD-883 Class B	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell	4.5 V	240	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 24 I/O	12	-55 °C (-67 °F)	Tin Lead	Quad	S-GQCC-J44		4.57 mm	16.51 mm	No	24 Macrocells	e0	20 MHz	24	220 °C (428 °F)	16.51 mm		24
5962-01-291-5582	Altera	UV PLD	Military	J Bend	68	QCCJ	Square	Ceramic	90 ns	Yes		48	CMOS	38535Q/M;38534H;883B			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No				1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)		Quad	S-XQCC-J68				No							No
EPF10K20QM240-4	Altera	Loadable PLD	Military	Gull Wing	240	FQFP	Square	Plastic/Epoxy	23.8 ns	Yes	5.5 V		CMOS				5		Flatpack, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G240		4.1 mm	32 mm	No	1152 Logic elements; Built-in JTAG boundry-scan test circuitry	e3	60.6 MHz			32 mm
EPM5130JM84	Altera	UV PLD	Military	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns	Yes	5.5 V		CMOS				5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	19 Dedicated Inputs, 48 I/O	19	-55 °C (-67 °F)		Quad	S-CQCC-J84		5.08 mm	29.21 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz			29.21 mm		48
EPF10K40QM240-4	Altera	Loadable PLD	Military	Gull Wing	240	FQFP	Square	Plastic/Epoxy	23.8 ns	Yes	5.5 V		CMOS				5		Flatpack, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G240		4.1 mm	32 mm	No	2304 Logic elements; Built-in JTAG boundry-scan test circuitry	e3	60.6 MHz			32 mm
5962-9473301MXC	Altera	Loadable PLD	Military	Pin/Peg	232	PGA	Square	Ceramic, Metal-Sealed Cofired		No	5.5 V		CMOS	MIL-STD-883			5		Grid Array				Registered	4.5 V		2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 180 I/O	4	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P232		5.207 mm	44.7 mm	No	1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e4			220 °C (428 °F)	44.7 mm		180
EP900JMB	Altera	UV PLD	Military	J Bend	44	WQCCJ	Square	Ceramic, Glass-Sealed	60 ns	Yes	5.5 V		CMOS		36	PAL-TYPE	5	5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices		Macrocell	4.5 V	240	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 24 I/O	12	-55 °C (-67 °F)	Tin Lead	Quad	S-GQCC-J44		4.57 mm	16.51 mm	No	24 Macrocells	e0	20 MHz	24	220 °C (428 °F)	16.51 mm		24
EPF10K40QM240-5	Altera	Loadable PLD	Military	Gull Wing	240	FQFP	Square	Plastic/Epoxy	27 ns	Yes	5.5 V		CMOS				5		Flatpack, Fine Pitch				Registered	4.5 V		.5 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)	Matte Tin	Quad	S-PQFP-G240		4.1 mm	32 mm	No	2304 Logic elements; Built-in JTAG boundry-scan test circuitry	e3	53.76 MHz			32 mm

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.