PGA Programmable Logic Devices (PLD) 304

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	No. of Logic Cells	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	No. of Inputs	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Maximum Time At Peak Reflow Temperature (s)	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
ISPLSI1032-60LG/883	Lattice Semiconductor	EE PLD	Military	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	25 ns		No	5.5 V	128	CMOS	MIL-STD-883		5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	Yes	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 64 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84		5.588 mm	29.464 mm	No	In-System Programmable; 4 External Clocks		38 MHz	30 s		225 °C (437 °F)	29.464 mm	No	64
ISPLSI1048C-50LG/883	Lattice Semiconductor	EE PLD	Military	Pin/Peg	133	PGA	Square	Ceramic, Metal-Sealed Cofired	26 ns		No	5.5 V	192	CMOS	MIL-STD-883		5	5 V	Grid Array	PGA132,14X14	Programmable Logic Devices	Yes	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	8 Dedicated Inputs, 96 I/O	8	-55 °C (-67 °F)		Perpendicular	S-CPGA-P133		5.588 mm	37.084 mm	No	In-System Programmable; 4 External Clocks		34.5 MHz	30 s		225 °C (437 °F)	37.084 mm	No	96
EP1810GM883B	Altera	OT PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	50 ns		No		48	CMOS	38535Q/M;38534H;883B		5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Perpendicular	S-XPGA-P68				No		e0				220 °C (428 °F)		No
EPM7192EGI160-20	Intel	EE PLD	Industrial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.5 V	192	CMOS			5	3.3/5,5 V	Grid Array	PGA160M,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 124 I/O	0	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P160	1	5.34 mm	39.624 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	83.3 MHz				39.624 mm	No	124
EPM7256EGI192-15	Intel	EE PLD	Industrial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	5.5 V	256	CMOS			5	3.3/5,5 V	Grid Array	PGA192M,17X17	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 160 I/O	0	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	76.9 MHz			220 °C (428 °F)	45.15 mm	No	160
EPM9560GC280-15	Altera	EE PLD	Commercial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	16.6 ns		No	5.25 V	560	CMOS			5	3.3/5,5 V	Grid Array	PGA280,19X19	Programmable Logic Devices	Yes	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 216 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P280	1	5.081 mm	49.78 mm	No	772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V	e0	117.6 MHz			220 °C (428 °F)	49.78 mm	Yes	216
EPM7192GC160-12	Altera	EE PLD	Commercial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	12 ns		No	5.25 V	192	CMOS			5	5 V	Grid Array	PGA160M,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 120 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P160	1	5.34 mm	39.624 mm	No	192 Macrocells; Shared Input/Clock	e0	90.9 MHz			220 °C (428 °F)	39.624 mm	No	120
EPM7256EGI192-20	Intel	EE PLD	Industrial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.5 V	256	CMOS			5	3.3/5,5 V	Grid Array	PGA192M,17X17	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 164 I/O	0	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	83.3 MHz				45.15 mm	No	164
EPM9560GI280-15	Intel	EE PLD	Industrial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	16.6 ns		No	5.5 V	560	CMOS			5	3.3/5,5 V	Grid Array	PGA280,19X19	Programmable Logic Devices	Yes	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 216 I/O	0	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P280	1	5.08 mm	49.78 mm	No	560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V	e0	117.6 MHz				49.78 mm	Yes	216
5962-8946803XX	Infineon Technologies	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	51 ns		No	5.5 V		CMOS	MIL-STD-883		5		Grid Array				Macrocell	4.5 V		125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68				No									52
XC7372-12PG84C	Xilinx	OT PLD	Commercial	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	28 ns		No	5.25 V	72	CMOS			5	3.3/5,5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 37 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P84		4.318 mm	27.94 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz				27.94 mm	No	37
XC73144-12PG184M	Xilinx	UV PLD	Military	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired			No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V		125 °C (257 °F)	0 Dedicated Inputs, 120 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture								120
XC73144-10PG184C	Xilinx	UV PLD	Commercial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired			No			CMOS			5		Grid Array				Macrocell			70 °C (158 °F)			0 °C (32 °F)		Perpendicular	S-CPGA-P184				No	PAL Blocks interconnected by PIA; 144 Macrocells; Configurable I/O operation with 3.3 V or 5 V
XC7372-10PG84C	Xilinx	OT PLD	Commercial	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	23 ns		No	5.25 V	72	CMOS			5	3.3/5,5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 37 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P84		4.318 mm	27.94 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		71.4 MHz				27.94 mm	No	37
XC7272-30PG84C	Xilinx	UV PLD	Commercial	Pin/Peg	84	PGA	Square	Ceramic	48 ns		No		72	CMOS			5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No			2.54 mm	70 °C (158 °F)			0 °C (32 °F)		Perpendicular	S-XPGA-P84				No								No
XC73144-10PG184M	Xilinx	UV PLD	Military	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired			No			CMOS			5		Grid Array				Macrocell			125 °C (257 °F)			-55 °C (-67 °F)		Perpendicular	S-CPGA-P184				No	PAL Blocks interconnected by PIA; 144 Macrocells; Configurable I/O operation with 3.3 V or 5 V
XC73144-15PG184I	Xilinx	UV PLD	Industrial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	36 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V		85 °C (185 °F)	0 Dedicated Inputs, 120 I/O	0	-40 °C (-40 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		45.5 MHz						120
XC73144-12PG184I	Xilinx	UV PLD	Industrial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	30 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V		85 °C (185 °F)	0 Dedicated Inputs, 120 I/O	0	-40 °C (-40 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		55.6 MHz						120
XC73144-12PG184C	Xilinx	UV PLD	Commercial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	30 ns		No	5.25 V		CMOS			5		Grid Array				Macrocell	4.75 V		70 °C (158 °F)	0 Dedicated Inputs, 120 I/O	0	0 °C (32 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		55.6 MHz						120
XC73144-10PG184I	Xilinx	UV PLD	Industrial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired			No			CMOS			5		Grid Array				Macrocell			85 °C (185 °F)			-40 °C (-40 °F)		Perpendicular	S-CPGA-P184				No	PAL Blocks interconnected by PIA; 144 Macrocells; Configurable I/O operation with 3.3 V or 5 V
XC7372-12PG84I	Xilinx	OT PLD	Industrial	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	28 ns		No	5.5 V	72	CMOS			5	3.3/5,5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 37 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		4.318 mm	27.94 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz				27.94 mm	No	37
XC7272-30PG84I	Xilinx	UV PLD	Industrial	Pin/Peg	84	PGA	Square	Ceramic	48 ns		No		72	CMOS			5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No			2.54 mm	85 °C (185 °F)			-40 °C (-40 °F)		Perpendicular	S-XPGA-P84				No								No
XC7372-15PG84I	Xilinx	OT PLD	Industrial	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	33 ns		No	5.5 V	72	CMOS			5	3.3/5,5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 37 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		4.318 mm	27.94 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz				27.94 mm	No	37
XC7272-25PG84C	Xilinx	UV PLD	Commercial	Pin/Peg	84	PGA	Square	Ceramic	40 ns		No		72	CMOS			5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No			2.54 mm	70 °C (158 °F)			0 °C (32 °F)		Perpendicular	S-XPGA-P84				No								No
XC7372-10PG84I	Xilinx	OT PLD	Industrial	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	23 ns		No	5.5 V	72	CMOS			5	3.3/5,5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 37 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		4.318 mm	27.94 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		71.4 MHz				27.94 mm	No	37
XC7272-25PG84I	Xilinx	UV PLD	Industrial	Pin/Peg	84	PGA	Square	Ceramic	40 ns		No		72	CMOS			5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No			2.54 mm	85 °C (185 °F)			-40 °C (-40 °F)		Perpendicular	S-XPGA-P84				No								No
XC73144-15PG184C	Xilinx	UV PLD	Commercial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	36 ns		No	5.25 V		CMOS			5		Grid Array				Macrocell	4.75 V		70 °C (158 °F)	0 Dedicated Inputs, 120 I/O	0	0 °C (32 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		45.5 MHz						120
XC73144-15PG184M	Xilinx	UV PLD	Military	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	36 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V		125 °C (257 °F)	0 Dedicated Inputs, 120 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		45.5 MHz						120
XC7372-15PG84C	Xilinx	OT PLD	Commercial	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	33 ns		No	5.25 V	72	CMOS			5	3.3/5,5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 37 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P84		4.318 mm	27.94 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz				27.94 mm	No	37
EPM7192SGC160-10	Altera	EE PLD	Commercial	Pin/Peg	160	PGA	Square	Ceramic	10 ns		No		192	CMOS				3.3/5,5 V	Grid Array	PGA160M,15X15	Programmable Logic Devices	Yes			2.54 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Perpendicular	S-XPGA-P160	1			No		e0				220 °C (428 °F)		Yes
EPM7256EGC192-12	Altera	EE PLD	Commercial	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	12 ns		No	5.25 V	256	CMOS			5	3.3/5,5 V	Grid Array	PGA192M,17X17	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 164 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P192	1	5.43 mm	45.15 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz			220 °C (428 °F)	45.15 mm	No	164
EPM9320GC280-15	Altera	EE PLD	Commercial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	16 ns		No	5.25 V	320	CMOS			5	3.3/5,5 V	Grid Array	PGA280,19X19	Programmable Logic Devices	Yes	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	0 Dedicated Inputs, 168 I/O	0	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P280	1	5.081 mm	49.78 mm	No	484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V	e0	117.6 MHz			220 °C (428 °F)	49.78 mm	Yes	168
EPM5128GI-2	Altera	UV PLD	Industrial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.5 V	128	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz			220 °C (428 °F)		No	52
EP1830GC-25	Altera	OT PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic	28 ns		No		48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Perpendicular	S-XPGA-P68	1			No		e0				220 °C (428 °F)		No
EPM9320GM280-12	Altera	EE PLD	Military	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	12 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 168 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	320 Macrocells; 484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz				49.78 mm		168
EPF8452GC160-2	Altera	Loadable PLD	Commercial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired		336	No	5.25 V		CMOS		120	5	3.3/5,5 V	Grid Array	QFP160,1.2SQ	Field Programmable Gate Arrays		Registered	4.75 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 116 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P160	1	5.34 mm	39.624 mm	No	452 Flip Flops; 336 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0			116	220 °C (428 °F)	39.624 mm		116
5962-01-324-9619	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	75 ns		No		48	CMOS	38535Q/M;38534H;883B		5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)		Perpendicular	S-XPGA-P68				No								No
EPF8452AGC160-A-3	Altera	Loadable PLD	Commercial	Pin/Peg	160	PGA	Square	Ceramic, Metal-Sealed Cofired	1.8 ns		No	3.6 V		CMOS			3.3		Grid Array				Registered	3 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 120 I/O	4	0 °C (32 °F)		Perpendicular	S-CPGA-P160		5.34 mm	39.624 mm	No	Can also operate at 5 V supply						39.624 mm		120
EPF81500GM280-2	Altera	Loadable PLD	Military	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired			No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 204 I/O	4	-55 °C (-67 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	1500 Flip Flops; 1296 Logic elements; Configurable I/O operation with 3.3 V or 5 V						49.78 mm		204
EPF81500GI280-3	Altera	Loadable PLD	Industrial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired			No	5.5 V		CMOS			5		Grid Array				Registered	4.5 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 204 I/O	4	-40 °C (-40 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	1500 Flip Flops; 1296 Logic elements; Configurable I/O operation with 3.3 V or 5 V						49.78 mm		204
5962-9206201MZX	Altera	UV PLD	Military	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	90 ns		No	5.5 V		CMOS	MIL-STD-883 Class B		5		Grid Array				Macrocell	4.5 V		125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84				No			19.6 MHz						64
EPF81188AGI232-A-3	Altera	Loadable PLD	Industrial	Pin/Peg	232	PGA	Square	Ceramic, Metal-Sealed Cofired	1.8 ns		No	3.6 V		CMOS			3.3		Grid Array				Registered	3 V	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 184 I/O	4	-40 °C (-40 °F)		Perpendicular	S-CPGA-P232		5.207 mm	44.7 mm	No	Can also operate at 5 V supply						44.7 mm		184
EP1810GC-20	Altera	UV PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	22 ns		No	5.25 V	48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	50 MHz			220 °C (428 °F)		No	48
EPM9400GI280-12	Altera	EE PLD	Industrial	Pin/Peg	280	PGA	Square	Ceramic, Metal-Sealed Cofired	12 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	0 Dedicated Inputs, 184 I/O	0	-40 °C (-40 °F)		Perpendicular	S-CPGA-P280		5.081 mm	49.78 mm	No	400 Macrocells; 580 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz				49.78 mm		184
EP1810GC-35	Altera	UV PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	40 ns		No	5.25 V	48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	28.6 MHz			220 °C (428 °F)		No	48
EPM7256EGM883B192-15	Altera	EE PLD	Military	Pin/Peg	192	PGA	Square	Ceramic, Metal-Sealed Cofired	15 ns		No	5.5 V		CMOS			5		Grid Array				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	0 Dedicated Inputs, 160 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P192		5.43 mm	45.15 mm	No	256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock		76.9 MHz				45.15 mm		160
EPF81188AGC232-4	Altera	Loadable PLD	Commercial	Pin/Peg	232	PGA	Square	Ceramic, Metal-Sealed Cofired		1008	No	5.25 V		CMOS		184	5	3.3/5,5 V	Grid Array	PGA232M,17X17	Field Programmable Gate Arrays		Registered	4.75 V	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 184 I/O	4	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P232	1	5.207 mm	44.7 mm	No	1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V	e0	357 MHz		180	220 °C (428 °F)	44.7 mm		184
5962-9206201MZC	Altera	UV PLD	Military	Pin/Peg	84	PGA	Square	Ceramic, Metal-Sealed Cofired	90 ns		No	5.5 V		CMOS	MIL-STD-883 Class B		5		Grid Array				Macrocell	4.5 V		125 °C (257 °F)	7 Dedicated Inputs, 64 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P84				No			19.6 MHz						64

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.