PGA Programmable Logic Devices (PLD) 304

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Part RoHS Manufacturer Programmable IC Type Grading Of Temperature Form Of Terminal No. of Terminals Package Code Package Shape Package Body Material Propagation Delay No. of Logic Cells Surface Mount Maximum Supply Voltage No. of Macro Cells Technology Used Screening Level No. of Inputs Architecture Nominal Supply Voltage (V) Packing Method Power Supplies (V) Package Style (Meter) Package Equivalence Code Sub-Category In-System Programmable Output Function Minimum Supply Voltage No. of Product Terms Pitch Of Terminal Maximum Operating Temperature Organization No. of Dedicated Inputs Minimum Operating Temperature Finishing Of Terminal Used Position Of Terminal JESD-30 Code Moisture Sensitivity Level (MSL) Maximum Seated Height Width Qualification Additional Features JESD-609 Code Maximum Clock Frequency Maximum Time At Peak Reflow Temperature (s) No. of Outputs Peak Reflow Temperature (C) Length JTAG Boundary Scan Test No. of I/O Lines

EPM7256EGC192-10

Altera

EE PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

10 ns

No

5.25 V

256

CMOS

5

3.3/5,5 V

Grid Array

PGA192M,17X17

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 160 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P192

1

5.43 mm

45.15 mm

No

Configurable I/O operation with 3.3 V or 5 V

e0

100 MHz

220 °C (428 °F)

45.15 mm

No

160

EPM7256GC192

Altera

UV PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic

25 ns

No

256

CMOS

5

5 V

Grid Array

PGA192M,17X17

Programmable Logic Devices

No

2.54 mm

70 °C (158 °F)

0 °C (32 °F)

Tin Lead

Perpendicular

S-XPGA-P192

1

No

e0

220 °C (428 °F)

No

EPF10K70GC504-5

Altera

Loadable PLD

Commercial

Pin/Peg

504

PGA

Square

Ceramic, Metal-Sealed Cofired

27 ns

No

5.25 V

CMOS

5

Grid Array

Registered

4.75 V

70 °C (158 °F)

4 Dedicated Inputs, 358 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P504

No

3744 Logic elements Configurable I/O operation with 3.3 V or 5 V

53.76 MHz

358

EPM7256EGM883B192-20

Altera

EE PLD

Military

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

20 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 160 I/O

0

-55 °C (-67 °F)

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

62.5 MHz

45.15 mm

160

EPM7192EGM883B160-15

Altera

EE PLD

Military

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 120 I/O

0

-55 °C (-67 °F)

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

76.9 MHz

39.624 mm

120

EPF8820G5962192-3

Altera

Loadable PLD

Military

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.5 V

CMOS

5

Grid Array

Registered

4.5 V

2.54 mm

125 °C (257 °F)

4 Dedicated Inputs, 148 I/O

4

-55 °C (-67 °F)

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V

45.15 mm

148

EPM7192EGM883B160-20

Altera

EE PLD

Military

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

20 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 120 I/O

0

-55 °C (-67 °F)

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

62.5 MHz

39.624 mm

120

EPM9320GI280-20

Altera

EE PLD

Industrial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

23 ns

No

5.5 V

320

CMOS

5

3.3/5,5 V

Grid Array

PGA280,19X19

Programmable Logic Devices

Yes

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

0 Dedicated Inputs, 168 I/O

0

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P280

1

5.08 mm

49.78 mm

No

484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V

e0

100 MHz

220 °C (428 °F)

49.78 mm

Yes

168

EPM7192EGM160-15

Altera

EE PLD

Military

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

192

CMOS

5

3.3/5,5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

Macrocell

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs

0

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

192 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

e0

76.9 MHz

220 °C (428 °F)

39.624 mm

No

EP20K1000EPC984-2

Altera

Loadable PLD

Other

Pin/Peg

984

PGA

Square

Ceramic, Metal-Sealed Cofired

No

1.89 V

1.8

Grid Array

Macrocell

1.71 V

85 °C (185 °F)

4 Dedicated Inputs, 716 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P984

No

160 MHz

716

EPM7192EGI160-10

Altera

EE PLD

Industrial

Pin/Peg

160

PGA

Square

Ceramic

10 ns

No

192

CMOS

3.3/5,5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

2.54 mm

85 °C (185 °F)

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-XPGA-P160

1

No

e0

220 °C (428 °F)

No

EPM7256EGI192-12

Altera

EE PLD

Industrial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

12 ns

No

5.5 V

256

CMOS

5

3.3/5,5 V

Grid Array

PGA192M,17X17

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

0 Dedicated Inputs, 164 I/O

0

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P192

1

5.43 mm

45.15 mm

No

256 Macrocells

e0

125 MHz

220 °C (428 °F)

45.15 mm

No

164

EP20K1500EPC984

Altera

Loadable PLD

Other

Pin/Peg

984

PGA

Square

Ceramic, Metal-Sealed Cofired

No

1.89 V

1.8

Grid Array

Macrocell

1.71 V

85 °C (185 °F)

4 Dedicated Inputs, 858 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P984

No

160 MHz

858

EPM7192EGI160-15

Altera

EE PLD

Industrial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.5 V

192

CMOS

5

3.3/5,5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

0 Dedicated Inputs, 120 I/O

0

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P160

1

5.34 mm

39.624 mm

No

Configurable I/O operation with 3.3 V or 5 V

e0

76.9 MHz

220 °C (428 °F)

39.624 mm

No

120

EPM5130GI

Altera

UV PLD

Industrial

Pin/Peg

100

PGA

Square

Ceramic, Metal-Sealed Cofired

55 ns

No

5.5 V

128

CMOS

5

5 V

Grid Array

PGA100M,13X13

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

19 Dedicated Inputs, 64 I/O

19

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P100

1

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

e0

33.3 MHz

220 °C (428 °F)

No

64

EPF10K100GI504-4

Altera

Loadable PLD

Industrial

Pin/Peg

504

PGA

Square

Ceramic, Metal-Sealed Cofired

23.8 ns

No

5.5 V

CMOS

5

Grid Array

Registered

4.5 V

85 °C (185 °F)

4 Dedicated Inputs, 406 I/O

4

-40 °C (-40 °F)

Perpendicular

S-CPGA-P504

No

4992 Logic elements Configurable I/O operation with 3.3 V or 5 V

60.6 MHz

406

EPM9560GM280-15

Altera

EE PLD

Military

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 216 I/O

0

-55 °C (-67 °F)

Perpendicular

S-CPGA-P280

5.081 mm

49.78 mm

No

560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V

117.6 MHz

49.78 mm

216

EPM9480GI280-15

Altera

EE PLD

Industrial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

0 Dedicated Inputs, 200 I/O

0

-40 °C (-40 °F)

Perpendicular

S-CPGA-P280

5.081 mm

49.78 mm

No

480 Macrocells; 676 Flip Flops; Configurable I/O operation with 3.3 V or 5 V

118 MHz

49.78 mm

200

EPF8452AGC160-A-2

Altera

Loadable PLD

Commercial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

1.7 ns

No

3.6 V

CMOS

3.3

Grid Array

Registered

3 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 120 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P160

5.34 mm

39.624 mm

No

Can also operate at 5 V supply

39.624 mm

120

EPM9480GM280-15

Altera

EE PLD

Military

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 200 I/O

0

-55 °C (-67 °F)

Perpendicular

S-CPGA-P280

5.081 mm

49.78 mm

No

480 Macrocells; 676 Flip Flops; Configurable I/O operation with 3.3 V or 5 V

118 MHz

49.78 mm

200

EP20K400GC655-1

Altera

Loadable PLD

Other

Pin/Peg

655

PGA

Square

Ceramic, Metal-Sealed Cofired

2.5 ns

16640

No

2.625 V

CMOS

496

2.5

2.5,2.5/3.3 V

Grid Array

SPGA655,47X47

Field Programmable Gate Arrays

Macrocell

2.375 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 502 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P655

1

4.08 mm

62.484 mm

No

e0

496

220 °C (428 °F)

62.484 mm

502

EPM7192GC160-20

Altera

EE PLD

Commercial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

20 ns

No

5.25 V

192

CMOS

5

5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 120 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P160

1

5.34 mm

39.624 mm

No

192 Macrocells; Shared Input/Clock

e0

62.5 MHz

220 °C (428 °F)

39.624 mm

No

120

EPF81500AGC280-2

Altera

Loadable PLD

Commercial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

1.7 ns

1296

No

3.6 V

CMOS

208

3.3

3.3/5,5 V

Grid Array

PGA280,19X19

Field Programmable Gate Arrays

Registered

3 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 208 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P280

1

5.081 mm

49.78 mm

No

Can also operate at 5 V supply

e0

417 MHz

204

220 °C (428 °F)

49.78 mm

208

EPM5130GI-2

Altera

UV PLD

Industrial

Pin/Peg

100

PGA

Square

Ceramic, Metal-Sealed Cofired

45 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

85 °C (185 °F)

19 Dedicated Inputs, 64 I/O

19

-40 °C (-40 °F)

Perpendicular

S-CPGA-P100

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

40 MHz

64

EPF8636AGC192-A-3

Altera

Loadable PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

1.8 ns

No

3.6 V

CMOS

3.3

Grid Array

Registered

3 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 136 I/O

4

0 °C (32 °F)

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

Can also operate at 5 V supply

45.15 mm

136

EPM9560GM280-20

Altera

EE PLD

Military

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

20 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 216 I/O

0

-55 °C (-67 °F)

Perpendicular

S-CPGA-P280

5.081 mm

49.78 mm

No

560 Macrocells; 772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V

95.2 MHz

49.78 mm

216

EP1830GC-30

Altera

OT PLD

Commercial

Pin/Peg

68

PGA

Square

Ceramic

34 ns

No

48

CMOS

5

5 V

Grid Array

PGA68,11X11

Programmable Logic Devices

No

2.54 mm

70 °C (158 °F)

0 °C (32 °F)

Tin Lead

Perpendicular

S-XPGA-P68

1

No

e0

220 °C (428 °F)

No

EP1800GM

Altera

UV PLD

Military

Pin/Peg

68

PGA

Square

Ceramic

90 ns

No

48

CMOS

5

5 V

Grid Array

PGA68,11X11

Programmable Logic Devices

No

2.54 mm

125 °C (257 °F)

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-XPGA-P68

No

e0

220 °C (428 °F)

No

EPF8820GM883B192-3

Altera

Loadable PLD

Military

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.5 V

CMOS

5

Grid Array

Registered

4.5 V

2.54 mm

125 °C (257 °F)

4 Dedicated Inputs, 148 I/O

4

-55 °C (-67 °F)

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V

45.15 mm

148

EPF81188AGI232-4

Altera

Loadable PLD

Industrial

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

1008

No

5.5 V

CMOS

184

5

3.3/5,5 V

Grid Array

PGA232M,17X17

Field Programmable Gate Arrays

Registered

4.5 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 180 I/O

4

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P232

1

5.207 mm

44.7 mm

No

1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

180

220 °C (428 °F)

44.7 mm

180

5962-9314401MYC

Altera

UV PLD

Military

Pin/Peg

100

PGA

Square

Ceramic, Metal-Sealed Cofired

75 ns

No

5.5 V

CMOS

MIL-STD-883 Class B

5

Grid Array

Macrocell

4.5 V

125 °C (257 °F)

19 Dedicated Inputs, 64 I/O

19

-55 °C (-67 °F)

Perpendicular

S-CPGA-P100

No

22.2 MHz

64

5962-01-407-9563

Altera

UV PLD

Military

Pin/Peg

68

PGA

Square

Ceramic

35 ns

No

128

CMOS

38535Q/M;38534H;883B

5

5 V

Grid Array

PGA68,11X11

Programmable Logic Devices

No

2.54 mm

125 °C (257 °F)

-55 °C (-67 °F)

Perpendicular

S-XPGA-P68

No

No

EPM5192GC-1

Altera

UV PLD

Commercial

Pin/Peg

84

PGA

Square

Ceramic, Metal-Sealed Cofired

40 ns

No

5.25 V

192

CMOS

5

5 V

Grid Array

PGA84M,11X11

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

7 Dedicated Inputs, 64 I/O

7

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P84

1

No

Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock

e0

50 MHz

220 °C (428 °F)

No

64

EP1810GI-20

Altera

UV PLD

Industrial

Pin/Peg

68

PGA

Square

Ceramic, Metal-Sealed Cofired

20 ns

No

5.5 V

5

Grid Array

Macrocell

4.5 V

85 °C (185 °F)

12 Dedicated Inputs, 48 I/O

12

-40 °C (-40 °F)

Perpendicular

S-CPGA-P68

No

62.5 MHz

48

5962-9324702MXC

Altera

EE PLD

Military

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

2.625 V

CMOS

MIL-STD-883

2.5

Grid Array

Macrocell

2.375 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs

0

-55 °C (-67 °F)

Gold

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

e4

76.9 MHz

220 °C (428 °F)

45.15 mm

EPF81188AGC232-2

Altera

Loadable PLD

Commercial

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

1008

No

5.25 V

CMOS

184

5

3.3/5,5 V

Grid Array

PGA232M,17X17

Field Programmable Gate Arrays

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 184 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P232

1

5.207 mm

44.7 mm

No

1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

417 MHz

180

220 °C (428 °F)

44.7 mm

184

EPM5192GI-1

Altera

UV PLD

Industrial

Pin/Peg

84

PGA

Square

Ceramic, Metal-Sealed Cofired

25 ns

No

5.5 V

CMOS

5

Grid Array

Macrocell

4.5 V

85 °C (185 °F)

7 Dedicated Inputs, 64 I/O

7

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P84

No

e0

62.5 MHz

64

EPF8820GI192-2

Altera

Loadable PLD

Industrial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.5 V

CMOS

5

Grid Array

Registered

4.5 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 148 I/O

4

-40 °C (-40 °F)

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

820 Flip Flops; 672 Logic elements; Configurable I/O operation with 3.3 V or 5 V

45.15 mm

148

EPM7256SGC192-10

Altera

EE PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic

10 ns

No

256

CMOS

3.3/5,5 V

Grid Array

PGA192M,17X17

Programmable Logic Devices

Yes

2.54 mm

70 °C (158 °F)

0 °C (32 °F)

Tin Lead

Perpendicular

S-XPGA-P192

1

No

e0

220 °C (428 °F)

Yes

EPF81188GI232-3

Altera

Loadable PLD

Industrial

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

1008

No

5.5 V

CMOS

184

5

3.3/5,5 V

Grid Array

PGA232,17X17

Field Programmable Gate Arrays

Registered

4.5 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 180 I/O

4

-40 °C (-40 °F)

Tin Lead

Perpendicular

S-CPGA-P232

1

5.207 mm

44.7 mm

No

1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

180

220 °C (428 °F)

44.7 mm

180

EPF81500GC280-2

Altera

Loadable PLD

Commercial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

1296

No

5.25 V

CMOS

208

5

3.3/5,5 V

Grid Array

PGA280,19X19

Field Programmable Gate Arrays

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 204 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P280

1

5.081 mm

49.78 mm

No

1500 Flip Flops; 1296 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

204

220 °C (428 °F)

49.78 mm

204

5962-9473301MXC

Altera

Loadable PLD

Military

Pin/Peg

232

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.5 V

CMOS

MIL-STD-883

5

Grid Array

Registered

4.5 V

2.54 mm

125 °C (257 °F)

4 Dedicated Inputs, 180 I/O

4

-55 °C (-67 °F)

Gold

Perpendicular

S-CPGA-P232

5.207 mm

44.7 mm

No

1188 Flip Flops; 1008 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e4

220 °C (428 °F)

44.7 mm

180

EPM7192EGC160-10P

Altera

EE PLD

Commercial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

10 ns

No

5.25 V

192

CMOS

5

3.3/5,5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 120 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P160

1

5.34 mm

39.624 mm

No

Configurable I/O operation with 3.3 V or 5 V

e0

100 MHz

220 °C (428 °F)

39.624 mm

No

120

EPF81500GI280-2

Altera

Loadable PLD

Industrial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

No

5.5 V

CMOS

5

Grid Array

Registered

4.5 V

2.54 mm

85 °C (185 °F)

4 Dedicated Inputs, 204 I/O

4

-40 °C (-40 °F)

Perpendicular

S-CPGA-P280

5.081 mm

49.78 mm

No

1500 Flip Flops; 1296 Logic elements; Configurable I/O operation with 3.3 V or 5 V

49.78 mm

204

EPF8636AGC192-3

Altera

Loadable PLD

Commercial

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

504

No

5.25 V

CMOS

136

5

3.3/5,5 V

Grid Array

PGA192M,17X17

Field Programmable Gate Arrays

Registered

4.75 V

2.54 mm

70 °C (158 °F)

4 Dedicated Inputs, 136 I/O

4

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P192

1

5.43 mm

45.15 mm

No

504 Logic elements; Configurable I/O operation with 3.3 V or 5 V

e0

385 MHz

132

220 °C (428 °F)

45.15 mm

136

EPM7256EGM192-15

Altera

EE PLD

Military

Pin/Peg

192

PGA

Square

Ceramic, Metal-Sealed Cofired

15 ns

No

5.5 V

256

CMOS

5

3.3/5,5 V

Grid Array

PGA192M,17X17

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

0 Dedicated Inputs, 160 I/O

0

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-CPGA-P192

5.43 mm

45.15 mm

No

256 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; Shared Input/Clock

e0

76.9 MHz

220 °C (428 °F)

45.15 mm

No

160

EPM9560GC280-20

Altera

EE PLD

Commercial

Pin/Peg

280

PGA

Square

Ceramic, Metal-Sealed Cofired

23.6 ns

No

5.25 V

560

CMOS

5

3.3/5,5 V

Grid Array

PGA280,19X19

Programmable Logic Devices

Yes

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 216 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P280

1

5.081 mm

49.78 mm

No

772 Flip Flops; Configurable I/O operation with 3.3 V or 5 V

e0

100 MHz

220 °C (428 °F)

49.78 mm

Yes

216

EPM7192EGC160-12P

Altera

EE PLD

Commercial

Pin/Peg

160

PGA

Square

Ceramic, Metal-Sealed Cofired

12 ns

No

5.25 V

192

CMOS

5

3.3/5,5 V

Grid Array

PGA160M,15X15

Programmable Logic Devices

No

Macrocell

4.75 V

2.54 mm

70 °C (158 °F)

0 Dedicated Inputs, 120 I/O

0

0 °C (32 °F)

Tin Lead

Perpendicular

S-CPGA-P160

1

5.34 mm

39.624 mm

No

Configurable I/O operation with 3.3 V or 5 V

e0

90.9 MHz

220 °C (428 °F)

39.624 mm

No

120

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.