Part | RoHS | Manufacturer | Programmable IC Type | Grading Of Temperature | Form Of Terminal | No. of Terminals | Package Code | Package Shape | Total Dose (V) | Package Body Material | No. of Logic Cells | Surface Mount | Maximum Supply Voltage | No. of CLBs | Technology Used | Screening Level | No. of Inputs | No. of Equivalent Gates | Nominal Supply Voltage (V) | Packing Method | Power Supplies (V) | Package Style (Meter) | Package Equivalence Code | Sub-Category | Minimum Supply Voltage | Pitch Of Terminal | Maximum Operating Temperature | Maximum Combinatorial Delay of a CLB | Organization | Minimum Operating Temperature | Finishing Of Terminal Used | Position Of Terminal | JESD-30 Code | Moisture Sensitivity Level (MSL) | Maximum Seated Height | Width | Qualification | Additional Features | JESD-609 Code | Maximum Clock Frequency | Maximum Time At Peak Reflow Temperature (s) | No. of Outputs | Peak Reflow Temperature (C) | Length |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Xilinx |
FPGA |
Commercial |
Ball |
676 |
BGA |
Square |
Plastic/Epoxy |
Yes |
1.89 V |
2400 |
CMOS |
129600 |
1.8 |
Grid Array |
1.71 V |
1 mm |
70 °C (158 °F) |
0.42 ns |
2400 CLBS, 129600 Gates |
0 °C (32 °F) |
Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) |
Bottom |
S-PBGA-B676 |
3 |
2.6 mm |
27 mm |
No |
e1 |
400 MHz |
30 s |
250 °C (482 °F) |
27 mm |
|||||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
No |
5.25 V |
144 |
CMOS |
96 |
3000 |
5 |
5 V |
Grid Array |
PGA132,14X14 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
4.1 ns |
144 CLBS, 3000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P132 |
3.9116 mm |
37.084 mm |
No |
MAX 96 I/OS; 480 flip-flops; typical gates = 3000 - 3700 |
190 MHz |
96 |
37.084 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
175 |
PGA |
Square |
Plastic/Epoxy |
No |
5.25 V |
320 |
CMOS |
9000 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
9 ns |
320 CLBS, 9000 Gates |
0 °C (32 °F) |
Perpendicular |
S-PPGA-P175 |
3.937 mm |
42.164 mm |
No |
MAX 144 I/OS; 928 flip-flops; power-down supplier current = 5 µA @ VCC = 3.2 V & T = 25°C |
70 MHz |
42.164 mm |
||||||||||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.25 V |
224 |
CMOS |
6400 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
9 ns |
224 CLBS, 6400 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P132 |
4.318 mm |
37.084 mm |
No |
MAX 110 I/OS; 688 flip-flops; power-down supplier current = 4 µA @ VCC = 3.2 V & T = 25°C |
70 MHz |
37.084 mm |
||||||||||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Plastic/Epoxy |
144 |
No |
5.25 V |
144 |
CMOS |
96 |
4200 |
5 |
5 V |
Grid Array |
PGA132,14X14 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
144 CLBS, 4200 Gates |
0 °C (32 °F) |
Tin Lead |
Perpendicular |
S-PPGA-P132 |
1 |
4.191 mm |
37.084 mm |
No |
MAX 96 I/OS; 480 flip-flops |
e0 |
50 MHz |
96 |
37.084 mm |
||||||||
Xilinx |
FPGA |
Commercial |
Ball |
484 |
FBGA |
Square |
Plastic/Epoxy |
74637 |
Yes |
1.05 V |
5831 |
328 |
1 |
Grid Array, Fine Pitch |
BGA484,22X22,32 |
.95 V |
.8 mm |
70 °C (158 °F) |
0.46 ns |
5831 CLBS |
0 °C (32 °F) |
Tin Lead |
Bottom |
S-PBGA-B484 |
3 |
1.8 mm |
19 mm |
e0 |
328 |
19 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
208 |
FQFP |
Square |
Plastic/Epoxy |
238 |
Yes |
5.25 V |
100 |
CMOS |
160 |
2500 |
5 |
5 V |
Flatpack, Fine Pitch |
QFP208,1.2SQ,20 |
Field Programmable Gate Arrays |
4.75 V |
.5 mm |
70 °C (158 °F) |
4 ns |
100 CLBS, 2500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G208 |
3 |
3.92 mm |
28 mm |
No |
MAX 160 I/OS; 200 flip-flops; typical gates = 2500 - 3000 |
e0 |
133.3 MHz |
30 s |
160 |
225 °C (437 °F) |
28 mm |
|||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
144 |
Yes |
3.6 V |
144 |
CMOS |
74 |
2000 |
3.3 |
3.3 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
3 V |
1.27 mm |
70 °C (158 °F) |
2.2 ns |
144 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
5.08 mm |
29.3116 mm |
No |
Typical gates = 2000-3000 |
e0 |
325 MHz |
30 s |
74 |
225 °C (437 °F) |
29.3116 mm |
|||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
484 |
Yes |
5.25 V |
484 |
CMOS |
138 |
6500 |
5 |
5 V |
Flatpack |
QFP160,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
.65 mm |
70 °C (158 °F) |
4.1 ns |
484 CLBS, 6500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G160 |
3 |
3.94 mm |
28 mm |
No |
MAX 176 I/OS; 1320 flip-flops; typical gates = 6500 - 9000 |
e0 |
190 MHz |
30 s |
138 |
225 °C (437 °F) |
28 mm |
|||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
44 |
TQFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
1024 |
CMOS |
3000 |
5 |
Flatpack, Thin Profile |
4.75 V |
.8 mm |
70 °C (158 °F) |
1024 CLBS, 3000 Gates |
0 °C (32 °F) |
Quad |
S-PQFP-G44 |
1.2 mm |
10 mm |
No |
512 flip-flops; 3.3 V operation; OTP based |
10 mm |
||||||||||||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
175 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.25 V |
320 |
CMOS |
9000 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
320 CLBS, 9000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P175 |
3.5052 mm |
42.164 mm |
No |
MAX 144 I/OS; 928 flip-flops; power-down supplier current = 5 µA @ VCC = 3.2 V & T = 25°C |
50 MHz |
42.164 mm |
|||||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.25 V |
1024 |
CMOS |
3000 |
5 |
Flatpack |
4.75 V |
.65 mm |
70 °C (158 °F) |
1024 CLBS, 3000 Gates |
0 °C (32 °F) |
Quad |
R-PQFP-G100 |
3.4 mm |
14 mm |
No |
512 flip-flops; 3.3 V operation; OTP based |
20 mm |
||||||||||||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Plastic/Epoxy |
No |
5.25 V |
224 |
CMOS |
6400 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
5.5 ns |
224 CLBS, 6400 Gates |
0 °C (32 °F) |
Perpendicular |
S-PPGA-P132 |
4.191 mm |
37.084 mm |
No |
MAX 110 I/OS; 688 flip-flops; power-down supplier current = 4 µA @ VCC = 3.2 V & T = 25°C |
125 MHz |
37.084 mm |
||||||||||||||||
|
Xilinx |
FPGA |
Commercial |
Ball |
676 |
BGA |
Square |
Plastic/Epoxy |
Yes |
1.89 V |
2400 |
CMOS |
129600 |
1.8 |
Grid Array |
1.71 V |
1 mm |
70 °C (158 °F) |
0.4 ns |
2400 CLBS, 129600 Gates |
0 °C (32 °F) |
Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) |
Bottom |
S-PBGA-B676 |
3 |
2.6 mm |
27 mm |
No |
e1 |
416 MHz |
30 s |
250 °C (482 °F) |
27 mm |
|||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
224 |
CMOS |
6400 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
7 ns |
224 CLBS, 6400 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J84 |
4.699 mm |
29.3116 mm |
No |
MAX 70 I/OS; 688 flip-flops; power-down supplier current = 4 µA @ VCC = 3.2 V & T = 25°C |
100 MHz |
29.3116 mm |
||||||||||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
175 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
484 |
No |
5.25 V |
484 |
CMOS |
144 |
6500 |
5 |
5 V |
Grid Array |
PGA175,16X16 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
4.1 ns |
484 CLBS, 6500 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P175 |
3.81 mm |
42.164 mm |
No |
MAX 176 I/OS; 1320 flip-flops; typical gates = 6500 - 9000 |
190 MHz |
144 |
42.164 mm |
|||||||||
|
Xilinx |
FPGA |
Commercial |
Ball |
676 |
BGA |
Square |
Plastic/Epoxy |
Yes |
1.89 V |
2400 |
CMOS |
129600 |
1.8 |
Grid Array |
1.71 V |
1 mm |
70 °C (158 °F) |
0.47 ns |
2400 CLBS, 129600 Gates |
0 °C (32 °F) |
Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5) |
Bottom |
S-PBGA-B676 |
3 |
2.6 mm |
27 mm |
No |
e1 |
357 MHz |
30 s |
250 °C (482 °F) |
27 mm |
|||||||||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.635 mm |
70 °C (158 °F) |
7 ns |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
100 MHz |
17.272 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
Ball |
484 |
BGA |
Square |
Plastic/Epoxy |
43661 |
Yes |
1.05 V |
3411 |
320 |
1 |
Grid Array |
BGA484,22X22,32 |
.95 V |
.8 mm |
70 °C (158 °F) |
0.46 ns |
3411 CLBS |
0 °C (32 °F) |
Tin Lead |
Bottom |
S-PBGA-B484 |
3 |
1.8 mm |
19 mm |
e0 |
320 |
19 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
224 |
CMOS |
6400 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
5.5 ns |
224 CLBS, 6400 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J84 |
4.699 mm |
29.3116 mm |
No |
MAX 70 I/OS; 688 flip-flops; power-down supplier current = 4 µA @ VCC = 3.2 V & T = 25°C |
125 MHz |
29.3116 mm |
||||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
44 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
34 |
2000 |
5 |
5 V |
Chip Carrier |
LDCC44,.7SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
2.7 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J44 |
3 |
4.318 mm |
16.5862 mm |
No |
MAX 80 I/OS; 360 flip-flops; typical gates = 2000 - 2700 |
e0 |
270 MHz |
30 s |
34 |
225 °C (437 °F) |
16.5862 mm |
|||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
175 |
PGA |
Square |
Plastic/Epoxy |
320 |
No |
5.25 V |
320 |
CMOS |
144 |
5000 |
5 |
5 V |
Grid Array |
PGA175,16X16 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
2.7 ns |
320 CLBS, 5000 Gates |
0 °C (32 °F) |
Perpendicular |
S-PPGA-P175 |
1 |
3.937 mm |
42.164 mm |
No |
MAX 144 I/OS; 928 flip-flops; typical gates = 5000 - 7500 |
270 MHz |
144 |
42.164 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
224 |
Yes |
5.25 V |
224 |
CMOS |
120 |
4000 |
5 |
5 V |
Flatpack |
QFP160,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
.65 mm |
70 °C (158 °F) |
4.1 ns |
224 CLBS, 4000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G160 |
3 |
3.94 mm |
28 mm |
No |
MAX 120 I/OS; 688 flip-flops; typical gates = 4000 - 5500 |
e0 |
190 MHz |
30 s |
120 |
225 °C (437 °F) |
28 mm |
|||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.635 mm |
70 °C (158 °F) |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
50 MHz |
17.272 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
4.699 mm |
29.3116 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
50 MHz |
29.3116 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
74 |
3000 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
100 CLBS, 3000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
4.699 mm |
29.3116 mm |
No |
MAX 74 I/OS; 360 flip-flops |
e0 |
50 MHz |
30 s |
74 |
225 °C (437 °F) |
29.3116 mm |
||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.25 V |
224 |
CMOS |
6400 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
5.5 ns |
224 CLBS, 6400 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P132 |
4.318 mm |
37.084 mm |
No |
MAX 110 I/OS; 688 flip-flops; power-down supplier current = 4 µA @ VCC = 3.2 V & T = 25°C |
125 MHz |
37.084 mm |
||||||||||||||||
Xilinx |
FPGA |
Commercial |
Ball |
484 |
BGA |
Square |
Plastic/Epoxy |
101261 |
Yes |
1.26 V |
7911 |
296 |
1.2 |
Grid Array |
BGA484,22X22,32 |
1.14 V |
.8 mm |
70 °C (158 °F) |
0.26 ns |
7911 CLBS |
0 °C (32 °F) |
Tin Lead |
Bottom |
S-PBGA-B484 |
3 |
1.8 mm |
19 mm |
e0 |
296 |
19 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
Through-Hole |
48 |
DIP |
Rectangular |
Plastic/Epoxy |
64 |
No |
5.25 V |
64 |
CMOS |
40 |
600 |
5 |
5 V |
In-Line |
DIP48,.6 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
15 ns |
64 CLBS, 600 Gates |
0 °C (32 °F) |
Tin Lead |
Dual |
R-PDIP-T48 |
1 |
4.826 mm |
15.24 mm |
No |
MAX 58 I/OS; 122 flip-flops; typical gates = 600 - 1000 |
e0 |
50 MHz |
40 |
61.7855 mm |
|||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
74 |
2000 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
2.7 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
4.699 mm |
29.3116 mm |
No |
MAX 80 I/OS; 360 flip-flops; typical gates = 2000 - 2700 |
e0 |
270 MHz |
30 s |
74 |
225 °C (437 °F) |
29.3116 mm |
|||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
144 |
LFQFP |
Square |
Plastic/Epoxy |
224 |
Yes |
3.6 V |
224 |
CMOS |
120 |
3500 |
3.3 |
3.3 V |
Flatpack, Low Profile, Fine Pitch |
QFP144,.87SQ,20 |
Field Programmable Gate Arrays |
3 V |
.5 mm |
70 °C (158 °F) |
6.7 ns |
224 CLBS, 3500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G144 |
3 |
1.6 mm |
20 mm |
No |
Max usable 4500 Logic gates |
e0 |
80 MHz |
30 s |
120 |
225 °C (437 °F) |
20 mm |
|||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
208 |
FQFP |
Square |
Metal |
1024 |
Yes |
5.25 V |
1024 |
CMOS |
256 |
20000 |
5 |
5 V |
Flatpack, Fine Pitch |
QFP208,1.2SQ,20 |
Field Programmable Gate Arrays |
4.75 V |
.5 mm |
70 °C (158 °F) |
4 ns |
1024 CLBS, 20000 Gates |
0 °C (32 °F) |
Quad |
S-MQFP-G208 |
1 |
3.94 mm |
27.64 mm |
No |
MAX 256 I/OS; 2560 flip-flops; Typical gates = 20000 - 25000 |
133.3 MHz |
256 |
27.64 mm |
|||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
120 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
No |
5.25 V |
144 |
CMOS |
95 |
3200 |
5 |
5 V |
Grid Array |
PGA120,13X13 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
4 ns |
144 CLBS, 3200 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P120 |
3.81 mm |
34.544 mm |
No |
MAX 96 I/OS; 480 flip-flops; typical gates = 3200 - 4000 |
133.3 MHz |
95 |
34.544 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Ball |
560 |
LBGA |
Square |
Plastic/Epoxy |
10800 |
Yes |
1.89 V |
2400 |
CMOS |
404 |
129600 |
1.8 |
1.2/3.6,1.8 V |
Grid Array, Low Profile |
BGA560,33X33,50 |
Field Programmable Gate Arrays |
1.71 V |
1.27 mm |
70 °C (158 °F) |
0.42 ns |
2400 CLBS, 129600 Gates |
0 °C (32 °F) |
Tin/Lead (Sn63Pb37) |
Bottom |
S-PBGA-B560 |
3 |
1.7 mm |
42.5 mm |
No |
e0 |
400 MHz |
30 s |
404 |
225 °C (437 °F) |
42.5 mm |
||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
208 |
FQFP |
Square |
Plastic/Epoxy |
320 |
Yes |
5.25 V |
320 |
CMOS |
144 |
5000 |
5 |
5 V |
Flatpack, Fine Pitch |
QFP208,1.2SQ,20 |
Field Programmable Gate Arrays |
4.75 V |
.5 mm |
70 °C (158 °F) |
3.3 ns |
320 CLBS, 5000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G208 |
3 |
3.92 mm |
28 mm |
No |
MAX 144 I/OS; 928 flip-flops; typical gates = 5000 - 7500 |
e0 |
230 MHz |
30 s |
144 |
225 °C (437 °F) |
28 mm |
|||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
64 |
Yes |
5.25 V |
64 |
CMOS |
64 |
2000 |
5 |
5 V |
Flatpack |
QFL100,.7SQ,25 |
Field Programmable Gate Arrays |
4.75 V |
.635 mm |
70 °C (158 °F) |
9 ns |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Quad |
S-CQFP-F100 |
1 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops |
70 MHz |
64 |
17.272 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Ball |
560 |
LBGA |
Square |
Plastic/Epoxy |
10800 |
Yes |
1.89 V |
2400 |
CMOS |
404 |
129600 |
1.8 |
1.2/3.6,1.8 V |
Grid Array, Low Profile |
BGA560,33X33,50 |
Field Programmable Gate Arrays |
1.71 V |
1.27 mm |
70 °C (158 °F) |
0.47 ns |
2400 CLBS, 129600 Gates |
0 °C (32 °F) |
Tin/Lead (Sn63Pb37) |
Bottom |
S-PBGA-B560 |
3 |
1.7 mm |
42.5 mm |
No |
e0 |
357 MHz |
30 s |
404 |
225 °C (437 °F) |
42.5 mm |
||||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
Yes |
5.25 V |
144 |
CMOS |
82 |
4200 |
5 |
5 V |
Flatpack |
QFL100,.7SQ,25 |
Field Programmable Gate Arrays |
4.75 V |
.635 mm |
70 °C (158 °F) |
9 ns |
144 CLBS, 4200 Gates |
0 °C (32 °F) |
Quad |
S-CQFP-F100 |
1 |
3.683 mm |
17.272 mm |
No |
MAX 82 I/OS; 480 flip-flops |
70 MHz |
82 |
17.272 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
320 |
Yes |
5.25 V |
320 |
CMOS |
70 |
9000 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
320 CLBS, 9000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
4.699 mm |
29.3116 mm |
No |
MAX 70 I/OS; 928 flip-flops |
e0 |
50 MHz |
30 s |
70 |
225 °C (437 °F) |
29.3116 mm |
||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
64 |
LFQFP |
Square |
Plastic/Epoxy |
Yes |
3.6 V |
64 |
CMOS |
3.3 |
Flatpack, Low Profile, Fine Pitch |
3 V |
.5 mm |
70 °C (158 °F) |
64 CLBS |
0 °C (32 °F) |
Quad |
S-PQFP-G64 |
1.27 mm |
10 mm |
No |
MAX 64 I/OS; 1300 to 7500 available gates |
10 mm |
|||||||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
208 |
FQFP |
Square |
Plastic/Epoxy |
320 |
Yes |
5.25 V |
320 |
CMOS |
144 |
5000 |
5 |
5 V |
Flatpack, Fine Pitch |
QFP208,1.2SQ,20 |
Field Programmable Gate Arrays |
4.75 V |
.5 mm |
70 °C (158 °F) |
2.7 ns |
320 CLBS, 5000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G208 |
3 |
3.92 mm |
28 mm |
No |
MAX 144 I/OS; 928 flip-flops; typical gates = 5000 - 7500 |
e0 |
270 MHz |
30 s |
144 |
225 °C (437 °F) |
28 mm |
|||||
Xilinx |
FPGA |
Commercial |
J Bend |
44 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
1024 |
CMOS |
3000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
1024 CLBS, 3000 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J44 |
4.572 mm |
16.5862 mm |
No |
512 flip-flops; 3.3 V operation; OTP based |
16.5862 mm |
||||||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
64 |
Yes |
CMOS |
58 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
No |
e0 |
325 MHz |
58 |
||||||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
320 |
CMOS |
9000 |
5 |
Flatpack |
4.75 V |
.65 mm |
70 °C (158 °F) |
9 ns |
320 CLBS, 9000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G160 |
4.1 mm |
28 mm |
No |
MAX 137 I/OS; 928 flip-flops; power-down supplier current = 5 µA @ VCC = 3.2 V & T = 25°C |
e0 |
70 MHz |
28 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
2688 |
CMOS |
8700 |
5 |
Flatpack |
4.75 V |
.65 mm |
70 °C (158 °F) |
5.5 ns |
2688 CLBS, 8700 Gates |
0 °C (32 °F) |
Quad |
S-PQFP-G160 |
4.1 mm |
28 mm |
No |
MAX 130 I/OS; MAX 1344 flip-flops; OTP based |
28 mm |
|||||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
384 |
CMOS |
1248 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
5.5 ns |
384 CLBS, 1248 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J84 |
5.08 mm |
29.3116 mm |
No |
MAX 61 I/OS; MAX 192 flip-flops; OTP based |
29.3116 mm |
|||||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
100 |
TFQFP |
Square |
Plastic/Epoxy |
144 |
Yes |
3.6 V |
144 |
CMOS |
82 |
2000 |
3.3 |
3.3 V |
Flatpack, Thin Profile, Fine Pitch |
TQFP100,.63SQ |
Field Programmable Gate Arrays |
3 V |
.5 mm |
70 °C (158 °F) |
2.7 ns |
144 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G100 |
3 |
1.2 mm |
14 mm |
No |
Typical gates = 2000-3000 |
e0 |
270 MHz |
30 s |
82 |
240 °C (464 °F) |
14 mm |
|||||
Xilinx |
FPGA |
Commercial |
Flat |
164 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.25 V |
320 |
CMOS |
9000 |
5 |
Flatpack |
4.75 V |
.635 mm |
70 °C (158 °F) |
320 CLBS, 9000 Gates |
0 °C (32 °F) |
Quad |
S-CQFP-F164 |
3.683 mm |
27.432 mm |
No |
MAX 142 I/OS; 928 flip-flops; power-down supplier current = 5 µA @ VCC = 3.2 V & T = 25°C |
50 MHz |
27.432 mm |
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits that are programmable by the user to perform specific logic functions. They consist of a matrix of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes FPGAs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.
FPGAs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the FPGA hardware. The resulting configuration data is then loaded onto the FPGA, allowing it to perform the desired logic functions.
FPGAs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.