Part | RoHS | Manufacturer | Programmable IC Type | Grading Of Temperature | Form Of Terminal | No. of Terminals | Package Code | Package Shape | Total Dose (V) | Package Body Material | No. of Logic Cells | Surface Mount | Maximum Supply Voltage | No. of CLBs | Technology Used | Screening Level | No. of Inputs | No. of Equivalent Gates | Nominal Supply Voltage (V) | Packing Method | Power Supplies (V) | Package Style (Meter) | Package Equivalence Code | Sub-Category | Minimum Supply Voltage | Pitch Of Terminal | Maximum Operating Temperature | Maximum Combinatorial Delay of a CLB | Organization | Minimum Operating Temperature | Finishing Of Terminal Used | Position Of Terminal | JESD-30 Code | Moisture Sensitivity Level (MSL) | Maximum Seated Height | Width | Qualification | Additional Features | JESD-609 Code | Maximum Clock Frequency | Maximum Time At Peak Reflow Temperature (s) | No. of Outputs | Peak Reflow Temperature (C) | Length |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
84 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.25 V |
64 |
CMOS |
2000 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P84 |
4.318 mm |
27.94 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e3 |
50 MHz |
27.94 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
Ball |
484 |
BGA |
Square |
Plastic/Epoxy |
101261 |
Yes |
1.05 V |
7911 |
338 |
1 |
Grid Array |
BGA484,22X22,32 |
.95 V |
.8 mm |
70 °C (158 °F) |
0.46 ns |
7911 CLBS |
0 °C (32 °F) |
Tin Lead |
Bottom |
S-PBGA-B484 |
3 |
1.8 mm |
19 mm |
e0 |
338 |
19 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
484 |
Yes |
5.25 V |
484 |
CMOS |
70 |
6500 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
3.3 ns |
484 CLBS, 6500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
4.699 mm |
29.3116 mm |
No |
MAX 176 I/OS; 1320 flip-flops; typical gates = 6500 - 9000 |
e0 |
230 MHz |
30 s |
70 |
225 °C (437 °F) |
29.3116 mm |
|||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Plastic/Epoxy |
No |
5.25 V |
224 |
CMOS |
6400 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
224 CLBS, 6400 Gates |
0 °C (32 °F) |
Perpendicular |
S-PPGA-P132 |
4.191 mm |
37.084 mm |
No |
MAX 110 I/OS; 688 flip-flops; power-down supplier current = 4 µA @ VCC = 3.2 V & T = 25°C |
50 MHz |
37.084 mm |
|||||||||||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
84 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.25 V |
100 |
CMOS |
3000 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
9 ns |
100 CLBS, 3000 Gates |
0 °C (32 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P84 |
4.318 mm |
27.94 mm |
No |
MAX 74 I/OS; 360 flip-flops; power-down supplier current = 2 µA @ VCC = 3.2 V & T = 25°C |
e3 |
70 MHz |
27.94 mm |
||||||||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
156 |
PGA |
Square |
Ceramic |
196 |
No |
CMOS |
112 |
5 |
5 V |
Grid Array |
PGA156,16X16 |
Field Programmable Gate Arrays |
2.54 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Perpendicular |
S-XPGA-P156 |
No |
110 MHz |
112 |
|||||||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
224 |
CMOS |
6400 |
5 |
Flatpack |
4.75 V |
.65 mm |
70 °C (158 °F) |
224 CLBS, 6400 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G160 |
4.1 mm |
28 mm |
No |
MAX 120 I/OS; 688 flip-flops; power-down supplier current = 4 µA @ VCC = 3.2 V & T = 25°C |
e0 |
50 MHz |
28 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
2688 |
Yes |
5.25 V |
2688 |
CMOS |
208 |
9000 |
5 |
3.3/5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
5.4 ns |
2688 CLBS, 9000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
5.08 mm |
29.3116 mm |
No |
1344 flip-flops; 3.3 V operation; OTP based |
e0 |
144 MHz |
30 s |
208 |
225 °C (437 °F) |
29.3116 mm |
|||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
144 |
Yes |
5.25 V |
144 |
CMOS |
74 |
3000 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
4.1 ns |
144 CLBS, 3000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
4.699 mm |
29.3116 mm |
No |
MAX 96 I/OS; 480 flip-flops; typical gates = 3000 - 3700 |
e0 |
190 MHz |
30 s |
74 |
225 °C (437 °F) |
29.3116 mm |
|||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
224 |
No |
5.25 V |
224 |
CMOS |
110 |
4000 |
5 |
5 V |
Grid Array |
PGA132,14X14 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
3.3 ns |
224 CLBS, 4000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P132 |
3.9116 mm |
37.084 mm |
No |
MAX 120 I/OS; 688 flip-flops; typical gates = 4000 - 5500 |
230 MHz |
110 |
37.084 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
1024 |
Yes |
5.25 V |
1024 |
CMOS |
128 |
3000 |
5 |
3.3/5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.75 V |
.65 mm |
70 °C (158 °F) |
5.4 ns |
1024 CLBS, 3000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
R-PQFP-G100 |
3 |
3.4 mm |
14 mm |
No |
512 flip-flops; 3.3 V operation; OTP based |
e0 |
144 MHz |
30 s |
128 |
225 °C (437 °F) |
20 mm |
|||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
100 |
CMOS |
3000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
9 ns |
100 CLBS, 3000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J68 |
4.699 mm |
24.2316 mm |
No |
MAX 58 I/OS; 360 flip-flops; power-down supplier current = 2 µA @ VCC = 3.2 V & T = 25°C |
e0 |
70 MHz |
24.2316 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.25 V |
144 |
CMOS |
4200 |
5 |
Flatpack |
4.75 V |
.635 mm |
70 °C (158 °F) |
7 ns |
144 CLBS, 4200 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
3.683 mm |
17.272 mm |
No |
MAX 82 I/OS; 480 flip-flops; power-down supplier current = 3 µA @ VCC = 3.2 V & T = 25°C |
e0 |
100 MHz |
17.272 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
224 |
Yes |
5.25 V |
224 |
CMOS |
120 |
4000 |
5 |
5 V |
Flatpack |
QFP160,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
.65 mm |
70 °C (158 °F) |
2.7 ns |
224 CLBS, 4000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G160 |
3 |
3.94 mm |
28 mm |
No |
MAX 120 I/OS; 688 flip-flops; typical gates = 4000 - 5500 |
e0 |
270 MHz |
30 s |
120 |
225 °C (437 °F) |
28 mm |
|||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
320 |
CMOS |
9000 |
5 |
Flatpack |
4.75 V |
.65 mm |
70 °C (158 °F) |
320 CLBS, 9000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQFP-G160 |
4.1 mm |
28 mm |
No |
MAX 137 I/OS; 928 flip-flops; power-down supplier current = 5 µA @ VCC = 3.2 V & T = 25°C |
e0 |
50 MHz |
28 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
320 |
CMOS |
9000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
320 CLBS, 9000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
4.699 mm |
29.3116 mm |
No |
MAX 70 I/OS; 928 flip-flops; power-down supplier current = 5 µA @ VCC = 3.2 V & T = 25°C |
e0 |
50 MHz |
29.3116 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
484 |
Yes |
5.25 V |
484 |
CMOS |
70 |
6500 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
4.1 ns |
484 CLBS, 6500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
4.699 mm |
29.3116 mm |
No |
MAX 176 I/OS; 1320 flip-flops; typical gates = 6500 - 9000 |
e0 |
190 MHz |
30 s |
70 |
225 °C (437 °F) |
29.3116 mm |
|||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
84 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
64 |
No |
5.25 V |
64 |
CMOS |
64 |
1000 |
5 |
5 V |
Grid Array |
PGA84M,11X11 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
3.3 ns |
64 CLBS, 1000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P84 |
5.207 mm |
27.94 mm |
No |
Typical gates = 1000-1500 |
227 MHz |
64 |
27.94 mm |
|||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
84 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
No |
5.25 V |
144 |
CMOS |
74 |
3000 |
5 |
5 V |
Grid Array |
PGA84M,11X11 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
4.1 ns |
144 CLBS, 3000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P84 |
4.318 mm |
27.94 mm |
No |
MAX 96 I/OS; 480 flip-flops; typical gates = 3000 - 3700 |
190 MHz |
74 |
27.94 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
224 |
Yes |
3.6 V |
224 |
CMOS |
70 |
3500 |
3.3 |
3.3 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
3 V |
1.27 mm |
70 °C (158 °F) |
6.7 ns |
224 CLBS, 3500 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
5.08 mm |
29.3116 mm |
No |
Max usable 4500 Logic gates |
e0 |
80 MHz |
30 s |
70 |
225 °C (437 °F) |
29.3116 mm |
|||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
144 |
CMOS |
4200 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
144 CLBS, 4200 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J84 |
4.699 mm |
29.3116 mm |
No |
MAX 74 I/OS; 480 flip-flops; power-down supplier current = 3 µA @ VCC = 3.2 V & T = 25°C |
50 MHz |
29.3116 mm |
|||||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
58 |
2000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
4.1 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
MAX 80 I/OS; 360 flip-flops; typical gates = 2000 - 2700 |
190 MHz |
58 |
24.2316 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
84 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
No |
5.25 V |
100 |
CMOS |
3000 |
5 |
Grid Array |
4.75 V |
2.54 mm |
70 °C (158 °F) |
100 CLBS, 3000 Gates |
0 °C (32 °F) |
Matte Tin |
Perpendicular |
S-CPGA-P84 |
4.318 mm |
27.94 mm |
No |
MAX 74 I/OS; 360 flip-flops; power-down supplier current = 2 µA @ VCC = 3.2 V & T = 25°C |
e3 |
50 MHz |
27.94 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
CMOS |
74 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
No |
e0 |
33 MHz |
30 s |
74 |
225 °C (437 °F) |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
80 |
2000 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
4.75 V |
.65 mm |
70 °C (158 °F) |
3.3 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
R-PQFP-G100 |
3 |
2.87 mm |
14 mm |
No |
MAX 80 I/OS; 360 flip-flops; typical gates = 2000 - 2700 |
e0 |
230 MHz |
30 s |
80 |
225 °C (437 °F) |
20 mm |
|||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
320 |
Yes |
5.25 V |
320 |
CMOS |
70 |
5000 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
3.3 ns |
320 CLBS, 5000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
4.699 mm |
29.3116 mm |
No |
MAX 144 I/OS; 928 flip-flops; typical gates = 5000 - 7500 |
e0 |
230 MHz |
30 s |
70 |
225 °C (437 °F) |
29.3116 mm |
|||||
Xilinx |
FPGA |
Commercial |
Ball |
560 |
LBGA |
Square |
Plastic/Epoxy |
10800 |
Yes |
1.89 V |
2400 |
CMOS |
404 |
129600 |
1.8 |
1.2/3.6,1.8 V |
Grid Array, Low Profile |
BGA560,33X33,50 |
Field Programmable Gate Arrays |
1.71 V |
1.27 mm |
70 °C (158 °F) |
0.4 ns |
2400 CLBS, 129600 Gates |
0 °C (32 °F) |
Tin/Lead (Sn63Pb37) |
Bottom |
S-PBGA-B560 |
3 |
1.7 mm |
42.5 mm |
No |
e0 |
416 MHz |
30 s |
404 |
225 °C (437 °F) |
42.5 mm |
||||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.635 mm |
70 °C (158 °F) |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
50 MHz |
17.272 mm |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
Ball |
560 |
LBGA |
Square |
Plastic/Epoxy |
21168 |
Yes |
1.89 V |
4704 |
CMOS |
404 |
254016 |
1.8 |
1.2/3.6,1.8 V |
Grid Array, Low Profile |
BGA560,33X33,50 |
Field Programmable Gate Arrays |
1.71 V |
1.27 mm |
70 °C (158 °F) |
0.4 ns |
4704 CLBS, 254016 Gates |
0 °C (32 °F) |
Tin/Lead (Sn63Pb37) |
Bottom |
S-PBGA-B560 |
3 |
1.7 mm |
42.5 mm |
No |
e0 |
416 MHz |
30 s |
404 |
225 °C (437 °F) |
42.5 mm |
||||||
Xilinx |
FPGA |
Commercial |
J Bend |
44 |
QCCJ |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
100 |
CMOS |
3000 |
5 |
Chip Carrier |
4.75 V |
1.27 mm |
70 °C (158 °F) |
9 ns |
100 CLBS, 3000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J44 |
4.318 mm |
16.5862 mm |
No |
MAX 34 I/OS; 360 flip-flops; power-down supplier current = 2 µA @ VCC = 3.2 V & T = 25°C |
e0 |
70 MHz |
16.5862 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
224 |
Yes |
CMOS |
70 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Quad |
S-PQCC-J84 |
No |
70 MHz |
70 |
||||||||||||||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
175 |
PGA |
Square |
Plastic/Epoxy |
484 |
No |
5.25 V |
484 |
CMOS |
144 |
6500 |
5 |
5 V |
Grid Array |
PGA175,16X16 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
4.1 ns |
484 CLBS, 6500 Gates |
0 °C (32 °F) |
Perpendicular |
S-PPGA-P175 |
1 |
3.937 mm |
42.164 mm |
No |
MAX 176 I/OS; 1320 flip-flops; typical gates = 6500 - 9000 |
190 MHz |
144 |
42.164 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Plastic/Epoxy |
144 |
No |
5.25 V |
144 |
CMOS |
96 |
3000 |
5 |
5 V |
Grid Array |
PGA132,14X14 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
3.3 ns |
144 CLBS, 3000 Gates |
0 °C (32 °F) |
Perpendicular |
S-PPGA-P132 |
1 |
3.7338 mm |
37.084 mm |
No |
MAX 96 I/OS; 480 flip-flops; typical gates = 3000 - 3700 |
230 MHz |
96 |
37.084 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
CMOS |
58 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
No |
100 MHz |
58 |
||||||||||||||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
223 |
PGA |
Square |
Ceramic |
2688 |
No |
CMOS |
208 |
3.3/5 V |
Grid Array |
PGA223,18X18 |
Field Programmable Gate Arrays |
2.54 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Perpendicular |
S-XPGA-P223 |
No |
144 MHz |
208 |
|||||||||||||||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
144 |
No |
5.25 V |
144 |
CMOS |
96 |
4200 |
5 |
5 V |
Grid Array |
PGA132,14X14 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
144 CLBS, 4200 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P132 |
4.318 mm |
37.084 mm |
No |
MAX 96 I/OS; 480 flip-flops |
50 MHz |
96 |
37.084 mm |
||||||||||
|
Xilinx |
FPGA |
Commercial |
Pin/Peg |
175 |
PGA |
Square |
Ceramic, Metal-Sealed Cofired |
320 |
No |
5.25 V |
320 |
CMOS |
144 |
9000 |
5 |
5 V |
Grid Array |
PGA176,16X16MOD |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
320 CLBS, 9000 Gates |
0 °C (32 °F) |
Perpendicular |
S-CPGA-P175 |
3.5052 mm |
42.164 mm |
No |
MAX 144 I/OS; 928 flip-flops |
50 MHz |
144 |
42.164 mm |
||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.65 mm |
70 °C (158 °F) |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Quad |
R-PQFP-G100 |
3.1496 mm |
14 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
50 MHz |
20 mm |
|||||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
144 |
Yes |
5.25 V |
144 |
CMOS |
61 |
3200 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
4 ns |
144 CLBS, 3200 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
4.699 mm |
29.3116 mm |
No |
MAX 96 I/OS; 480 flip-flops; typical gates = 3200 - 4000 |
e0 |
133.3 MHz |
30 s |
61 |
225 °C (437 °F) |
29.3116 mm |
|||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
160 |
QFP |
Square |
Plastic/Epoxy |
196 |
Yes |
CMOS |
112 |
5 |
5 V |
Flatpack |
QFP160,1.2SQ |
Field Programmable Gate Arrays |
.635 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Tin/Lead (Sn85Pb15) |
Quad |
S-PQFP-G160 |
3 |
No |
e0 |
110 MHz |
30 s |
112 |
225 °C (437 °F) |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
238 |
Yes |
CMOS |
61 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
No |
e0 |
110 MHz |
30 s |
61 |
225 °C (437 °F) |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
Flat |
100 |
QFF |
Square |
Ceramic, Metal-Sealed Cofired |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.635 mm |
70 °C (158 °F) |
9 ns |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Tin Lead |
Quad |
S-CQFP-F100 |
3.683 mm |
17.272 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
e0 |
70 MHz |
17.272 mm |
||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
84 |
QCCJ |
Square |
Plastic/Epoxy |
196 |
Yes |
CMOS |
112 |
5 |
5 V |
Chip Carrier |
LDCC84,1.2SQ |
Field Programmable Gate Arrays |
1.27 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Tin Lead |
Quad |
S-PQCC-J84 |
3 |
No |
e0 |
110 MHz |
30 s |
112 |
225 °C (437 °F) |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
J Bend |
68 |
QCCJ |
Square |
Plastic/Epoxy |
100 |
Yes |
5.25 V |
100 |
CMOS |
58 |
2000 |
5 |
5 V |
Chip Carrier |
LDCC68,1.0SQ |
Field Programmable Gate Arrays |
4.75 V |
1.27 mm |
70 °C (158 °F) |
2.7 ns |
100 CLBS, 2000 Gates |
0 °C (32 °F) |
Quad |
S-PQCC-J68 |
1 |
4.445 mm |
24.2316 mm |
No |
MAX 80 I/OS; 360 flip-flops; typical gates = 2000 - 2700 |
270 MHz |
58 |
24.2316 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
144 |
Yes |
CMOS |
82 |
5 |
5 V |
Flatpack |
QFP100,.7X.9 |
Field Programmable Gate Arrays |
.635 mm |
70 °C (158 °F) |
0 °C (32 °F) |
Tin Lead |
Quad |
R-PQFP-G100 |
3 |
No |
e0 |
100 MHz |
30 s |
82 |
225 °C (437 °F) |
|||||||||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
100 |
QFP |
Rectangular |
Plastic/Epoxy |
Yes |
5.25 V |
64 |
CMOS |
2000 |
5 |
Flatpack |
4.75 V |
.65 mm |
70 °C (158 °F) |
7 ns |
64 CLBS, 2000 Gates |
0 °C (32 °F) |
Quad |
R-PQFP-G100 |
3.1496 mm |
14 mm |
No |
MAX 64 I/OS; 256 flip-flops; power-down supplier current = 1 µA @ VCC = 3.2 V & T = 25°C |
100 MHz |
20 mm |
||||||||||||||||
Xilinx |
FPGA |
Commercial |
Pin/Peg |
132 |
PGA |
Square |
Plastic/Epoxy |
224 |
No |
5.25 V |
224 |
CMOS |
110 |
4000 |
5 |
5 V |
Grid Array |
PGA132,14X14 |
Field Programmable Gate Arrays |
4.75 V |
2.54 mm |
70 °C (158 °F) |
4.1 ns |
224 CLBS, 4000 Gates |
0 °C (32 °F) |
Perpendicular |
S-PPGA-P132 |
1 |
3.7338 mm |
37.084 mm |
No |
MAX 120 I/OS; 688 flip-flops; typical gates = 4000 - 5500 |
190 MHz |
110 |
37.084 mm |
|||||||||
Xilinx |
FPGA |
Commercial |
Gull Wing |
44 |
TQFP |
Square |
Plastic/Epoxy |
Yes |
5.25 V |
384 |
CMOS |
1000 |
5 |
Flatpack, Thin Profile |
4.75 V |
.8 mm |
70 °C (158 °F) |
384 CLBS, 1000 Gates |
0 °C (32 °F) |
Quad |
S-PQFP-G44 |
1.2 mm |
10 mm |
No |
192 flip-flops; 3.3 V operation; OTP based |
10 mm |
Field Programmable Gate Arrays (FPGAs) are digital integrated circuits that are programmable by the user to perform specific logic functions. They consist of a matrix of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes FPGAs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.
FPGAs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the FPGA hardware. The resulting configuration data is then loaded onto the FPGA, allowing it to perform the desired logic functions.
FPGAs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.