J Bend Programmable Logic Devices (PLD) 2,387

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	No. of Logic Cells	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	No. of Inputs	Architecture	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	No. of Product Terms	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Maximum Time At Peak Reflow Temperature (s)	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EPM5016LC-20	Altera	OT PLD	Commercial	J Bend	20	QCCJ	Square	Plastic/Epoxy	20 ns		Yes	5.25 V		CMOS	16	PAL-TYPE	5	5 V	Chip Carrier	LDCC20,.4SQ	Programmable Logic Devices		Macrocell	4.75 V	160	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 8 I/O	7	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J20		4.572 mm	9.017 mm	No	Macrocells interconnected by PIA; 16 Macrocells; 1 External Clock; Shared Input/Clock	e0	62.5 MHz		8	220 °C (428 °F)	9.017 mm		8
EPM7096LI84-15	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.5 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 64 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84	3	5.08 mm	29.3116 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	100 MHz			220 °C (428 °F)	29.3116 mm	No	64
EPM7032LC44-15	Altera	EE PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.25 V	32	CMOS			5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 36 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44	1	4.572 mm	16.5862 mm	No	Labs interconnected by PIA; 2 Labs; 32 Macrocells; 1 External Clock; Shared Input/Clock	e0	100 MHz	20 s		220 °C (428 °F)	16.5862 mm	No	36
EP900LI-3	Altera	OT PLD	Industrial	J Bend	44	QCCJ	Square	Plastic/Epoxy	50 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 24 I/O	12	-40 °C (-40 °F)		Quad	S-PQCC-J44			16.6116 mm	No	24 Macrocells		23.8 MHz				16.6116 mm		24
EPX740LC44-12	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	15 ns	40	Yes	5.25 V		CMOS	32		5	5 V	Chip Carrier	LDCC44,.7SQ	Field Programmable Gate Arrays		Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 30 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.57 mm	16.5862 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	58.8 MHz		32	220 °C (428 °F)	16.5862 mm		30
EPM5128JM	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns		Yes		128	CMOS			5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell			1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz			220 °C (428 °F)	24.13 mm	No	52
EP1810JM5962-45	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	50 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J68		4.826 mm	24.13 mm	No	48 Macrocells; 4 External Clocks; Shared Input/Clock		22.2 MHz				24.13 mm		48
EPM7096SLC84-7	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	5.25 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 60 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz			220 °C (428 °F)	29.3116 mm	No	60
EP1810LC-35T	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	28.6 MHz			220 °C (428 °F)	24.23 mm	No	48
EPM7032SLI44-6	Altera	EE PLD	Industrial	J Bend	44	QCCJ	Square	Plastic/Epoxy	6 ns		Yes	5.5 V	32	CMOS			5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	Yes	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 36 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J44		4.57 mm	16.5862 mm	No	32 Macrocells	e0	200 MHz			220 °C (428 °F)	16.5862 mm	Yes	36
EP610ALM-10	Altera	OT PLD	Military	J Bend	28	QCCJ	Square	Plastic/Epoxy	10 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)		Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No	Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks		100 MHz				11.5062 mm		16
EPM7064SLC44-7F	Altera	EE PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	5.25 V	64	CMOS			5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 36 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.57 mm	16.5862 mm	No		e0	166.7 MHz			220 °C (428 °F)	16.5862 mm	Yes	36
EPM7160SLC84-6N	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	6 ns		Yes	5.25 V	160	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 64 I/O	0	0 °C (32 °F)	Matte Tin	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	160 Macrocells; 10 Labs; Configurable I/O operation with 3.3 V or 5 V	e3	166.7 MHz				29.3116 mm	Yes	64
EPF8282AVLC84-5	Altera	Loadable PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy			Yes	3.6 V		CMOS			3.3		Chip Carrier				Registered	3 V		1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 64 I/O	4	0 °C (32 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	282 Flip Flops; 208 Logic elements; Built-in JTAG boundry-scan test circuitry					220 °C (428 °F)	29.3116 mm		64
EP1830LC-30	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	34 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No				1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				220 °C (428 °F)		No
EP910ILC44-15	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.25 V		CMOS	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell	4.75 V	240	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 24 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.57 mm	16.5862 mm	No	24 Macrocells; 2 External Clocks	e0	100 MHz		24	220 °C (428 °F)	16.5862 mm		24
EPM7096LC84	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	25 ns		Yes	5.25 V	96	CMOS			5	5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 64 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No		e0				220 °C (428 °F)	29.3116 mm	No	64
EPF8636ALI84-5	Altera	Loadable PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy			Yes	5.5 V		CMOS			5		Chip Carrier				Registered	4.5 V		1.27 mm	85 °C (185 °F)	4 Dedicated Inputs, 64 I/O	4	-40 °C (-40 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V						29.3116 mm		64
EPM5192LI84-1	Altera	OT PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	40 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 64 I/O	7	-40 °C (-40 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	192 Macrocells; 12 Labs		62.5 MHz				29.3116 mm		64
EPM5128JM5962	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-CQCC-J68		4.826 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz				24.13 mm		52
EPM9320LC84-20H	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	23 ns		Yes	5.25 V	320	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 60 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No		e0				220 °C (428 °F)	29.3116 mm	Yes	60
EP910ALC-10	Altera		Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	10 ns		Yes			CMOS	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell		240	1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44				No		e0			24	220 °C (428 °F)
EPM7096JC84-2	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.25 V	96	CMOS			5	5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 64 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No		e0				220 °C (428 °F)	29.3116 mm	No	64
EPS448LI28-20	Altera	OT PLD	Industrial	J Bend	28	QCCJ	Square	Plastic/Epoxy			Yes	5.5 V		CMOS			5		Chip Carrier				Registered	4.5 V		1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 0 I/O	8	-40 °C (-40 °F)		Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No	PLS		20 MHz				11.5062 mm		0
EPM5130LI84	Altera	OT PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	55 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	19 Dedicated Inputs, 48 I/O	19	-40 °C (-40 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz				29.3116 mm		48
EP610LC-15T	Altera	OT PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	17 ns		Yes	5.25 V		CMOS	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.75 V	160	1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J28		4.57 mm	11.5062 mm	No	Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks	e0	71.4 MHz		16	220 °C (428 °F)	11.5062 mm		16
EPM5192ALI84-20	Altera	OT PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	33 ns		Yes	5.5 V	192	CMOS			5	5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 64 I/O	7	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock	e0	66.7 MHz			220 °C (428 °F)	29.3116 mm	No	64
EPM5128ALI68-12	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	20 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz				24.2316 mm		52
EP610ALI28-15	Altera	EE PLD	Industrial	J Bend	28	QCCJ	Square	Plastic/Epoxy	16 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	4 Dedicated Inputs, 16 I/O	4	-40 °C (-40 °F)		Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No	16 Macrocells; 2 External Clocks		71.4 MHz				11.5062 mm		16
EP610ILI28-10	Altera	OT PLD	Industrial	J Bend	28	QCCJ	Square	Plastic/Epoxy	10 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V		1.27 mm	85 °C (185 °F)	4 Dedicated Inputs, 16 I/O	4	-40 °C (-40 °F)		Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No	16 Macrocells; 2 External Clocks		125 MHz				11.5062 mm		16
EPF8452ALM84-4	Altera	Loadable PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy			Yes	5.5 V		CMOS			5		Chip Carrier				Registered	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 64 I/O	4	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	452 Flip Flops; 336 Logic Elements						29.3116 mm		64
EPM7128AELI84-12	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	12 ns		Yes	3.6 V	128	CMOS			3.3	2.5/3.3,3.3 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	3 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 68 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No		e0	100 MHz			220 °C (428 °F)	29.3116 mm	Yes	68
EP610ILC-10	Altera	OT PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.25 V		CMOS	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.75 V	160	1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J28				No		e0	100 MHz		16	220 °C (428 °F)			16
EP1800JC-1	Altera	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	90 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells	e0	25 MHz			220 °C (428 °F)	24.13 mm	No	48
EPM5016LM-20	Altera		Military	J Bend	20	QCCJ	Square	Plastic/Epoxy	20 ns		Yes			CMOS	16	PAL-TYPE	5	5 V	Chip Carrier	LDCC20,.4SQ	Programmable Logic Devices				160	1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-PQCC-J20				No		e0			8	220 °C (428 °F)
EPF8282VLI84-3	Altera	Loadable PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy			Yes			CMOS			3.3		Chip Carrier				Registered			1.27 mm	85 °C (185 °F)	4 Dedicated Inputs, 64 I/O	4	-40 °C (-40 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	282 Flip Flops; 208 Logic elements; Built-in JTAG boundry-scan test circuitry						29.3116 mm		64
EP610LC-20	Altera	OT PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	22 ns		Yes	5.25 V		CMOS	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.75 V	160	1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J28				No	Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks	e0	55.6 MHz		16	220 °C (428 °F)			16
EPM5032LC	Altera		Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	25 ns		Yes			CMOS	24	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices				320	1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J28				No		e0	62.5 MHz		16	220 °C (428 °F)
EPM5192LC-2	Altera	OT PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	45 ns		Yes	5.25 V	192	CMOS			5	5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e0	50 MHz			220 °C (428 °F)	29.3116 mm	No	64
EPF8282AVLI84-5	Altera	Loadable PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy			Yes	3.6 V		CMOS			3.3		Chip Carrier				Registered	3 V		1.27 mm	85 °C (185 °F)	4 Dedicated Inputs, 64 I/O	4	-40 °C (-40 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	282 Flip Flops; 208 Logic elements; Built-in JTAG boundry-scan test circuitry					220 °C (428 °F)	29.3116 mm		64
EP1800LC-35T	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	35 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No				1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				220 °C (428 °F)		No
EPM5128ALC-12	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	20 ns		Yes		128	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No				1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				220 °C (428 °F)		No
EPX740LC44-10	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	12 ns	40	Yes	5.25 V		CMOS	32		5	5 V	Chip Carrier	LDCC44,.7SQ	Field Programmable Gate Arrays		Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 30 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.57 mm	16.5862 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	71.4 MHz		32	220 °C (428 °F)	16.5862 mm		30
EPM7128SLI84-7	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	5.5 V	128	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 68 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	128 Macrocells	e0	166.7 MHz			220 °C (428 °F)	29.3116 mm	Yes	68
EPF8636ALM84-3	Altera	Loadable PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy			Yes	5.5 V		CMOS			5		Chip Carrier				Registered	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 64 I/O	4	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	636 Flip Flops; 504 Logic elements; Configurable I/O operation with 3.3 V or 5 V						29.3116 mm		64
EPM7032JC44-3	Altera	EE PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy			Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 36 I/O	0	0 °C (32 °F)		Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No							16.5862 mm		36
EPM7128ALI84-7	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	3.6 V	128	CMOS			3.3	2.5/3.3,3.3 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	3 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 68 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	128 Macrocells	e0	116.3 MHz			220 °C (428 °F)	29.3116 mm	Yes	68
EPM5032JC28-25	Altera	UV PLD	Commercial	J Bend	28	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns		Yes	5.25 V		CMOS			5		Chip Carrier, Window				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 16 I/O	7	0 °C (32 °F)		Quad	S-CQCC-J28		4.57 mm	11.43 mm	No	32 Macrocells; Shared Input/Clock; Shared Product Terms		50 MHz			220 °C (428 °F)	11.43 mm		16

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.