J Bend Programmable Logic Devices (PLD) 2,387

Reset All

Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	No. of Logic Cells	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	No. of Inputs	Architecture	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	No. of Product Terms	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Maximum Time At Peak Reflow Temperature (s)	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EPM7160SLI84-6	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	6 ns		Yes	5.5 V	160	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 64 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	160 Macrocells	e0	200 MHz			220 °C (428 °F)	29.3116 mm	Yes	64
EPM5064JM	Altera	UV PLD	Military	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns		Yes		64	CMOS			5	5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell			1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 28 I/O	7	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J44		4.57 mm	16.51 mm	No	Labs interconnected by PIA; 4 Labs; 64 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz			220 °C (428 °F)	16.51 mm	No	28
EPM5128LC	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	55 ns		Yes	5.25 V	128	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin/Lead	Quad	S-PQCC-J68				No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz	30 s		220 °C (428 °F)		No	52
EPM5032JM883B-25	Altera	UV PLD	Military	J Bend	28	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 16 I/O	7	-55 °C (-67 °F)		Quad	S-CQCC-J28		4.826 mm	11.43 mm	No	Macrocells interconnected by PIA; 1 LAB; 32 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz				11.43 mm		16
EP910LI-15	Altera	OT PLD	Industrial	J Bend	44	QCCJ	Square	Plastic/Epoxy			Yes	5.5 V					5		Chip Carrier				Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 24 I/O	12	-40 °C (-40 °F)		Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No							16.5862 mm		24
EPM7096LC84-12	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	12 ns		Yes	5.25 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 64 I/O	0	0 °C (32 °F)	Tin/Lead	Quad	S-PQCC-J84	3	5.08 mm	29.3116 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz	30 s		220 °C (428 °F)	29.3116 mm	No	64
EPF8636ALC84-A-4	Altera	Loadable PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	1.9 ns		Yes	3.6 V		CMOS			3.3		Chip Carrier				Registered	3 V		1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 68 I/O	4	0 °C (32 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Can also operate at 5 V supply						29.3116 mm		68
EPM5192AJC84-15	Altera	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns		Yes	5.25 V	192	CMOS			5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J84		5.08 mm	29.21 mm	No	Labs interconnected by PIA; 12 Labs; 1 External Clock	e0	83.3 MHz			220 °C (428 °F)	29.21 mm	No	64
EPM7032LI44-15	Altera	EE PLD	Industrial	J Bend	44	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.5 V	32	CMOS			5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 36 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J44	1	4.572 mm	16.5862 mm	No	Labs interconnected by PIA; 2 Labs; 32 Macrocells; 1 External Clock; Shared Input/Clock	e0	100 MHz			220 °C (428 °F)	16.5862 mm	No	36
EP630JC-20	Altera		Commercial	J Bend	28	QCCJ	Square	Ceramic	22 ns		Yes			CMOS	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell		160	1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-XQCC-J28				No		e0	55.5 MHz		16	220 °C (428 °F)
EPM7032AELC44-4	Altera	EE PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	4.5 ns		Yes	3.6 V	32	CMOS			3.3	2.5/3.3,3.3 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	Yes	Macrocell	3 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 36 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44	1	4.57 mm	16.5862 mm	No	32 Macrocells; 2 Labs; Configurable I/O operation with 2.5 V or 3.3 V	e0	227.3 MHz	20 s		220 °C (428 °F)	16.5862 mm	Yes	36
EP610LI-12	Altera	OT PLD	Industrial	J Bend	28	QCCJ	Square	Plastic/Epoxy			Yes	5.5 V					5		Chip Carrier				Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	4 Dedicated Inputs, 16 I/O	4	-40 °C (-40 °F)		Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No							11.5062 mm		16
EPM7064LC84-12	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	12 ns		Yes	5.25 V	64	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 68 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84	2	5.08 mm	29.3116 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz	20 s		220 °C (428 °F)	29.3116 mm	No	68
MPM5128LC	Altera	Mask PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	55 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz			220 °C (428 °F)	24.2316 mm		52
EP1830JI-30	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Ceramic	34 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No				1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Quad	S-XQCC-J68				No		e0				220 °C (428 °F)		No
EPM5130JC84-2	Altera	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	45 ns		Yes	5.25 V		CMOS			5		Chip Carrier, Window				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	19 Dedicated Inputs, 48 I/O	19	0 °C (32 °F)		Quad	S-CQCC-J84		5.08 mm	29.21 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		40 MHz				29.21 mm		48
EPM7064SLI44-6N	Altera	EE PLD	Industrial	J Bend	44	QCCJ	Square	Plastic/Epoxy	6 ns		Yes		64	CMOS			5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	Yes				1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)		Quad	S-PQCC-J44				No								No
EPM7160SLC84-7N	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	5.25 V	160	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 64 I/O	0	0 °C (32 °F)	Matte Tin	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Configurable I/O operation with 3.3 V or 5 V	e3	166.7 MHz				29.3116 mm	Yes	64
EPF10K10LC84-5	Altera	Loadable PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	27 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Registered	4.75 V		1.27 mm	70 °C (158 °F)	4 Dedicated Inputs	4	0 °C (32 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	576 Logic elements; Built-in JTAG boundry-scan test circuitry		53.76 MHz				29.3116 mm
EP630JM-20	Altera		Military	J Bend	28	QCCJ	Square	Ceramic	22 ns		Yes			CMOS	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell		160	1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-XQCC-J28				No		e0	55.5 MHz		16	220 °C (428 °F)
EPM5130JM-2	Altera	UV PLD	Military	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	45 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	19 Dedicated Inputs, 48 I/O	19	-55 °C (-67 °F)		Quad	S-CQCC-J84		5.08 mm	29.21 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		40 MHz				29.21 mm		48
EP1800LC-2	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	70 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68			24.2316 mm	No	48 Macrocells	e0	20.8 MHz			220 °C (428 °F)	24.2316 mm	No	48
EPX740LC44-10Z	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	12 ns	40	Yes	5.25 V		CMOS	32		5	5 V	Chip Carrier	LDCC44,.7SQ	Field Programmable Gate Arrays		Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 30 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.57 mm	16.5862 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	71.4 MHz		32	220 °C (428 °F)	16.5862 mm		30
EP900LC-3	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	50 ns		Yes	5.25 V		CMOS	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell	4.75 V	240	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 24 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44			16.6116 mm	No	24 Macrocells	e0	23.8 MHz		24	220 °C (428 °F)	16.6116 mm		24
EPM5064LC44-1	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	40 ns		Yes	5.25 V	64	CMOS			5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 28 I/O	7	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.57 mm	16.5862 mm	No	64 Macrocells; Shared Input/Clock; Shared Product Terms	e0	50 MHz			220 °C (428 °F)	16.5862 mm	No	28
EP600JMB	Altera	UV PLD	Military	J Bend	28	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns		Yes	5.5 V		CMOS	20	PAL-TYPE	5	5 V	Chip Carrier, Window	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.5 V	160	1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J28		4.57 mm	11.43 mm	No	16 Macrocells	e0	22.2 MHz		16	220 °C (428 °F)	11.43 mm		16
EPM7064AELC44-7N	Altera	EE PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	3.6 V		CMOS			3.3		Chip Carrier				Macrocell	3 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 36 I/O	0	0 °C (32 °F)	Matte Tin	Quad	S-PQCC-J44		4.57 mm	16.5862 mm	No	64 MICROCELLS; 4 Labs; Configurable I/O operation with 2.5 V or 3.3 V	e3	135.1 MHz				16.5862 mm		36
EPM5128LC-2	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	45 ns		Yes	5.25 V	128	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz			220 °C (428 °F)		No	52
EP324LC-25	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	25 ns		Yes	5.25 V		CMOS	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell	4.75 V	394	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 24 I/O	8	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44				No	24 Macrocells	e0	66 MHz		24	220 °C (428 °F)			24
EPM9320LM84-12	Altera	EE PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	12 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	0 Dedicated Inputs, 55 I/O	0	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	320 Macrocells; 484 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz				29.3116 mm		55
EPX740LC68-10Z	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	12 ns	40	Yes	5.25 V		CMOS	52		5	5 V	Chip Carrier	LDCC68,1.0SQ	Field Programmable Gate Arrays		Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 40 I/O	10	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	71.4 MHz		52	220 °C (428 °F)	24.23 mm		40
EPM7032AELC44-10N	Altera	EE PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	10 ns		Yes	3.6 V	32	CMOS			3.3	2.5/3.3,3.3 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	Yes	Macrocell	3 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 36 I/O	0	0 °C (32 °F)	Matte Tin	Quad	S-PQCC-J44	3	4.57 mm	16.5862 mm	No	32 Macrocells; 2 Labs; Configurable I/O operation with 2.5 V or 3.3 V	e3	103.1 MHz	30 s		245 °C (473 °F)	16.5862 mm	Yes	36
MPS464LC-20	Altera	Mask PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	20 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 32 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No	Macrocells Interconnected By Global Bus; Synchronous Timing Generator; 64 Macrocells	e0	66.7 MHz			220 °C (428 °F)	16.5862 mm		32
EPM5192JC84	Altera	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns		Yes	5.25 V		CMOS			5		Chip Carrier, Window				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)		Quad	S-CQCC-J84		5.08 mm	29.21 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz				29.21 mm		64
EP910ALC-12	Altera		Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	12 ns		Yes			CMOS	36	PAL-TYPE	5	5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell		240	1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44				No		e0			24	220 °C (428 °F)
EP610LI-20	Altera	OT PLD	Industrial	J Bend	28	QCCJ	Square	Plastic/Epoxy	22 ns		Yes	5.5 V		CMOS	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.5 V	160	1.27 mm	85 °C (185 °F)	4 Dedicated Inputs, 16 I/O	4	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J28				No	Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks	e0	55.6 MHz		16	220 °C (428 °F)			16
EPM7064AELI84-7	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	3.6 V	64	CMOS			3.3	2.5/3.3,3.3 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	3 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 68 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	64 Macrocells	e0	166.7 MHz			220 °C (428 °F)	29.3116 mm	Yes	68
EP600ILC-45	Altera	OT PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	45 ns		Yes	5.25 V					5		Chip Carrier				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J28		4.3688 mm	11.5316 mm		Seated HGT-NOM	e0	26.3 MHz			220 °C (428 °F)	11.5316 mm
EPM9400LM84-12	Altera	EE PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	12 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	0 Dedicated Inputs, 59 I/O	0	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	400 Macrocells; 580 Flip Flops; Configurable I/O operation with 3.3 V or 5 V		118 MHz				29.3116 mm		59
EPF10K20LM84-4	Altera	Loadable PLD	Military	J Bend	84	QCCJ	Square	Plastic/Epoxy	23.8 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Registered	4.5 V		1.27 mm	125 °C (257 °F)	4 Dedicated Inputs	4	-55 °C (-67 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	1152 Logic elements; Built-in JTAG boundry-scan test circuitry		60.6 MHz				29.3116 mm
EP1210LC	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	90 ns		Yes	5.25 V		CMOS	36	PAL-TYPE	5		Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices		Macrocell	4.75 V	236	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 24 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44			16.6116 mm	No	28 Macrocells	e0	17.5 MHz		24	220 °C (428 °F)	16.6116 mm		24
EPM5192JC-2	Altera	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	45 ns		Yes	5.25 V	192	CMOS			5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J84		5.08 mm	29.21 mm	No	Labs interconnected by PIA; 12 Labs; 192 Macrocells; 1 External Clock; Shared Input/Clock	e0	50 MHz			220 °C (428 °F)	29.21 mm	No	64
EP610LC28-35	Altera	OT PLD	Commercial	J Bend	28	QCCJ	Square	Plastic/Epoxy	37 ns		Yes	5.25 V		CMOS	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.75 V	160	1.27 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J28		4.572 mm	11.5062 mm	No	16 Macrocells; 2 External Clocks	e0	37 MHz		16	220 °C (428 °F)	11.5062 mm		16
EPS464LC-25	Altera	OT PLD	Commercial	J Bend	44	QCCJ	Square	Plastic/Epoxy	25 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 32 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J44		4.572 mm	16.5862 mm	No	Macrocells Interconnected By Global Bus; Synchronous Timing Generator; 64 Macrocells	e0	50 MHz			220 °C (428 °F)	16.5862 mm		32
EPM7128ELC84-12H	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	12 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 68 I/O	0	0 °C (32 °F)		Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No			125 MHz				29.3116 mm		68
EPM7128ALI84-6	Altera	EE PLD	Industrial	J Bend	84	QCCJ	Square	Plastic/Epoxy	6 ns		Yes	3.6 V	128	CMOS			3.3	2.5/3.3,3.3 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	3 V		1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 68 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	128 Macrocells	e0	144.9 MHz			220 °C (428 °F)	29.3116 mm	Yes	68
EPS464JC44-25	Altera	UV PLD	Commercial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns		Yes	5.25 V		CMOS			5		Chip Carrier, Window				Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 32 I/O	0	0 °C (32 °F)		Quad	S-CQCC-J44		4.57 mm	16.51 mm	No	64 Macrocells; Shared Input/Clock; Shared Product Terms		50 MHz				16.51 mm		32
EPM7160SLC84-15	Altera	EE PLD	Commercial	J Bend	84	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.25 V	160	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 60 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J84		5.08 mm	29.3116 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	76.9 MHz			220 °C (428 °F)	29.3116 mm	Yes	60

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.