68 Programmable Logic Devices (PLD) 419

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	No. of Logic Cells	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	No. of Inputs	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EPM5128GM883B-2	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No		128	CMOS	38535Q/M;38534H;883B		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz		220 °C (428 °F)	27.94 mm	No	52
EPM7096JC68-2	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.25 V	96	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No		e0			220 °C (428 °F)	24.2316 mm	No	52
EPM7096LC68-6	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	6 ns		Yes	5.25 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 48 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	151.5 MHz		220 °C (428 °F)	24.23 mm	No	48
EP1810JI-40	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Ceramic	45 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Quad	S-XQCC-J68				No		e0			220 °C (428 °F)		No
EP1810GC68-25	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	28 ns		No	5.25 V		CMOS			5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		50 MHz			27.94 mm		48
EPM5128AJI68-12	Altera	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	20 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz			24.13 mm		52
EPM5128ALI68-20	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	33 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz			24.2316 mm		52
EP1810LC68-20	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	22 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	48 Macrocells; Shared Input/Clock	e0	62.5 MHz		220 °C (428 °F)	24.2316 mm	No	48
EP1810GM883B-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks		22.2 MHz			27.94 mm		48
EP1810JC68-45	Altera	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	50 ns		Yes	5.25 V		CMOS			5		Chip Carrier, Window				Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells; Shared Input/Clock		22.2 MHz			24.13 mm		48
EP1810GC68-20	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	22 ns		No	5.25 V		CMOS			5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		62.5 MHz			27.94 mm		48
EP1810LC68-45	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	50 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	48 Macrocells; Shared Input/Clock	e0	33.3 MHz		220 °C (428 °F)	24.2316 mm	No	48
EPM7096SLI68-15	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.5 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 48 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	76.9 MHz		220 °C (428 °F)	24.23 mm	No	48
EPM5128GC68-2	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns		No	5.25 V		CMOS			5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		40 MHz			27.94 mm		52
EP1830GM-30	Altera	OT PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	34 ns		No		48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Perpendicular	S-XPGA-P68				No		e0			220 °C (428 °F)		No
EPM7096LC68-7	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	5.25 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	3	5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	166.7 MHz		220 °C (428 °F)	24.2316 mm	No	52
EP1810LM-45	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Plastic/Epoxy	50 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks		22.2 MHz			24.23 mm		48
EP1810JC-20	Altera	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	22 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	50 MHz		220 °C (428 °F)	24.13 mm	No	48
EP1810GM-45/883	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V		CMOS	MIL-STD-883		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks		22.2 MHz			27.94 mm		48
EPM5128JC68-2	Altera	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	45 ns		Yes	5.25 V		CMOS			5		Chip Carrier, Window				Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		40 MHz			24.13 mm		52
EPM5128AGC68-20	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns		No	5.25 V		CMOS			5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz			27.94 mm		52
EP1800GM-3	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	80 ns		No	5.5 V	48	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.0038 mm	27.94 mm	No	48 Macrocells	e0	18.5 MHz		220 °C (428 °F)	27.94 mm	No	48
EP1810GI68-25	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	28 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		50 MHz			27.94 mm		48
EPM7064LI68-6	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	6 ns		Yes	5.5 V	64	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 52 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	64 Macrocells	e0	200 MHz		220 °C (428 °F)	24.23 mm	No	52
EP1810JI68-25	Altera	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	28 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells; Shared Input/Clock		40 MHz			24.13 mm		48
EPM5128GM	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No		128	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz		220 °C (428 °F)	27.94 mm	No	52
EP1800JM883B	Altera	UV PLD	Military	J Bend	68	QCCJ	Square	Ceramic	90 ns		Yes		48	CMOS	38535Q/M;38534H;883B		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-XQCC-J68				No		e0			220 °C (428 °F)		No
EPM7096SLC68-10	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns		Yes	5.25 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 48 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	100 MHz		220 °C (428 °F)	24.23 mm	No	48
EPX740LI68-12	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns	40	Yes	5.5 V		CMOS		52	5	5 V	Chip Carrier	LDCC68,1.0SQ	Field Programmable Gate Arrays		Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	10 Dedicated Inputs, 40 I/O	10	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	58.8 MHz	52	220 °C (428 °F)	24.23 mm		40
EP1830GC-20	Altera	OT PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic	22 ns		No		48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Perpendicular	S-XPGA-P68	1			No		e0			220 °C (428 °F)		No
EP1810JC-40	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Ceramic	45 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-XQCC-J68				No		e0			220 °C (428 °F)		No
5962-8946804XC	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P68		3.81 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e4	66.7 MHz			27.94 mm		52
EPM5128AGI68-20	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz			27.94 mm		52
EPM5128LC-1	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns		Yes	5.25 V	128	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	50 MHz		220 °C (428 °F)		No	52
5962-8946901XA	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	50 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V		125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J68				No	48 Macrocells; 4 External Clocks; Shared Input/Clock	e0	22.2 MHz					48
5M80ZM68A5N	Altera	Flash PLD	Industrial	Ball	68	FBGA	Square	Plastic/Epoxy	14 ns		Yes		64	CMOS	AEC-Q100			1.8,1.2/3.3 V	Grid Array, Fine Pitch	BGA68,9X9,20	Programmable Logic Devices	Yes			.5 mm	105 °C (221 °F)			-40 °C (-40 °F)		Bottom	S-PBGA-B68				No							Yes
EP1830LC-20	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	22 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	48 Macrocells; 4 External Clocks; Shared Input/Clock	e0	50 MHz		220 °C (428 °F)	24.2316 mm	No	48
MPM5128LC-1	Altera	Mask PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns		Yes	5.25 V		CMOS			5		Chip Carrier				Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz		220 °C (428 °F)	24.2316 mm		52
EP1810LI68-20	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	22 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	48 Macrocells; Shared Input/Clock		62.5 MHz			24.2316 mm		48
EP1800JC-3	Altera	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	80 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells	e0	18.5 MHz		220 °C (428 °F)	24.13 mm	No	48
EPM5128LI-1	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Quad	S-PQCC-J68		5.08 mm	24.23 mm	No			62.5 MHz			24.23 mm		52
EPM5128ALM-20	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Plastic/Epoxy	33 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		66.7 MHz			24.23 mm		52
EP1810GC-35	Altera	UV PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	40 ns		No	5.25 V	48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	28.6 MHz		220 °C (428 °F)		No	48
EPX740LC68-15	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	18 ns	40	Yes	5.25 V		CMOS		52	5	5 V	Chip Carrier	LDCC68,1.0SQ	Field Programmable Gate Arrays		Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 40 I/O	10	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	50 MHz	52	220 °C (428 °F)	24.23 mm		40
EPM7096SLC68-7	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	5.25 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 48 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz		220 °C (428 °F)	24.23 mm	No	48
EP1800LC	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic	90 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0			220 °C (428 °F)		No
5M160ZM68C5	Altera	Flash PLD	Other	Ball	68	TFBGA	Square	Plastic/Epoxy	14 ns		Yes	1.89 V	128	CMOS			1.8	1.2/3.3,1.8 V	Grid Array, Thin Profile, Fine Pitch	BGA68,9X9,20	Programmable Logic Devices	Yes	Macrocell	1.71 V	.5 mm	85 °C (185 °F)	52 I/O		0 °C (32 °F)	Tin Lead	Bottom	S-PBGA-B68		1.2 mm	5 mm	No		e0	118.3 MHz			5 mm	Yes	52
EP1800JI	Altera	UV PLD	Industrial	J Bend	68	QCCJ	Square	Ceramic	90 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Quad	S-XQCC-J68				No		e0			220 °C (428 °F)		No

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.