68 Programmable Logic Devices (PLD) 419

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	No. of Logic Cells	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	No. of Inputs	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Maximum Time At Peak Reflow Temperature (s)	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
EPX740LC68-15Z	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	18 ns	40	Yes	5.25 V		CMOS		52	5	5 V	Chip Carrier	LDCC68,1.0SQ	Field Programmable Gate Arrays		Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 40 I/O	10	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	50 MHz		52	220 °C (428 °F)	24.23 mm		40
EPM7064LI68-10	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns		Yes	5.5 V	64	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 48 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	100 MHz			220 °C (428 °F)	24.2316 mm	No	48
EPM5128JI	Altera	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns		Yes	5.5 V	128	CMOS			5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz			220 °C (428 °F)	24.13 mm	No	52
EPM5128LM	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Plastic/Epoxy	55 ns		Yes	5.5 V	128	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz			220 °C (428 °F)	24.23 mm	No	52
EPM5128GI	Altera	UV PLD	Industrial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V	128	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz			220 °C (428 °F)		No	52
EPM7064SLI68-7	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	7.5 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 48 I/O	0	-40 °C (-40 °F)		Quad	S-PQCC-J68		5.08 mm	24.23 mm	No			166.7 MHz				24.23 mm		48
EPM5128JC68	Altera	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns		Yes	5.25 V		CMOS			5		Chip Carrier, Window				Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz				24.13 mm		52
EP1810LC-40	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	45 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				220 °C (428 °F)		No
EP1800ILC-70	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic	70 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				220 °C (428 °F)		No
EPM5128AGM68-15	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		83.3 MHz				27.94 mm		52
EP1800ILC-90	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic	90 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				220 °C (428 °F)		No
5962-8946901XX	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	50 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V		125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J68				No	48 Macrocells; 4 External Clocks; Shared Input/Clock		22.2 MHz						48
EPM5128JM883B	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns		Yes		128	CMOS	38535Q/M;38534H;883B		5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell		1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz			220 °C (428 °F)	24.13 mm	No	52
EP1810LC-55	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy			Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				220 °C (428 °F)		No
EPM7064SLC68-15	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns		Yes	5.25 V	64	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 48 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	76.9 MHz			220 °C (428 °F)	24.23 mm	No	48
EPM5128ALM68-12	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Plastic/Epoxy	20 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz				24.2316 mm		52
EP1830LI-25	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	48 Macrocells; 4 External Clocks; Shared Input/Clock		40 MHz				24.2316 mm		48
EP1810GM883B68-45	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		22.2 MHz				27.94 mm		48
EPM7096SLI68-10	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns		Yes	5.5 V	96	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 48 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	100 MHz			220 °C (428 °F)	24.23 mm	No	48
EPM5128GM5962	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz				27.94 mm		52
EP1810LC68-25T	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	48 Macrocells; Shared Input/Clock	e0	40 MHz			220 °C (428 °F)	24.2316 mm	No	48
EPM240ZM68I7N	Altera	Flash PLD		Ball	68	BGA	Rectangular	Plastic/Epoxy	12 ns		Yes	1.89 V	192	CMOS			1.8	1.5/3.3,1.8 V	Grid Array	BGA68,9X9,20	Programmable Logic Devices	Yes	Macrocell	1.71 V	.5 mm		0 Dedicated Inputs	0		Tin Silver Copper	Bottom	R-PBGA-B68				No	It can also operate at 3.3 V	e1						Yes
EPM7064LC68-10	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns		Yes	5.25 V	64	CMOS			5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	2	5.08 mm	24.2316 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	125 MHz	20 s		220 °C (428 °F)	24.2316 mm	No	52
EP1810JM68-45	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	50 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells; Shared Input/Clock		22.2 MHz				24.13 mm		48
EP1810LC-25	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	40 MHz			220 °C (428 °F)		No	48
5962-8854901YC	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square		85 ns		No	5.5 V		CMOS	MIL-STD-883		5		Grid Array				Macrocell	4.5 V		125 °C (257 °F)	11 Dedicated Inputs, 48 I/O	11	-55 °C (-67 °F)		Perpendicular	S-XPGA-P68				No			12.2 MHz						48
EP1800JMB	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	90 ns		Yes	5.5 V	48	CMOS			5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells	e0				220 °C (428 °F)	24.13 mm	No	48
EP1810LC-20	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	22 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	50 MHz			220 °C (428 °F)		No	48
EP1800ILC-75	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic	75 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				220 °C (428 °F)		No
EP1830JC-25	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Ceramic	28 ns		Yes		48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-XQCC-J68				No		e0				220 °C (428 °F)		No
EP1810GI-25	Altera	UV PLD	Industrial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	28 ns		No	5.5 V	48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	40 MHz			220 °C (428 °F)		No	48
EP1800GC-3	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	80 ns		No	5.25 V	48	CMOS			5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	5.0038 mm	27.94 mm	No	48 Macrocells	e0	18.5 MHz			220 °C (428 °F)	27.94 mm	No	48
5962-01-324-9619	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	75 ns		No		48	CMOS	38535Q/M;38534H;883B		5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)		Perpendicular	S-XPGA-P68				No								No
EPM5128AJM68-20	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz				24.13 mm		52
EPM5128LM68	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Plastic/Epoxy	55 ns		Yes	5.5 V		CMOS			5		Chip Carrier				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz				24.2316 mm		52
EPX740LC68-12	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns	40	Yes	5.25 V		CMOS		52	5	5 V	Chip Carrier	LDCC68,1.0SQ	Field Programmable Gate Arrays		Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 40 I/O	10	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	58.8 MHz		52	220 °C (428 °F)	24.23 mm		40
EPX740LC68-10	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	12 ns	40	Yes	5.25 V		CMOS		52	5	5 V	Chip Carrier	LDCC68,1.0SQ	Field Programmable Gate Arrays		Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 40 I/O	10	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	4 Labs; 40 Macrocells Configurable I/O operation with 3.3 V or 5 V	e0	71.4 MHz		52	220 °C (428 °F)	24.23 mm		40
EP1830LC-25	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		4.572 mm	24.2316 mm	No	48 Macrocells; 4 External Clocks; Shared Input/Clock	e0	40 MHz			220 °C (428 °F)	24.2316 mm	No	48
EP1800JM-3	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired			Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 48 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells		18.5 MHz				24.13 mm		48
EP1800JC-2	Altera	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	70 ns		Yes	5.25 V	48	CMOS			5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells	e0	20.8 MHz			220 °C (428 °F)	24.13 mm	No	48
EP1810GC-20	Altera	UV PLD	Commercial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	22 ns		No	5.25 V	48	CMOS			5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Macrocells Interconnected By Global And/Or Local Bus; 48 Macrocells; 4 External Clocks	e0	50 MHz			220 °C (428 °F)		No	48
EPM7096JC68	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	25 ns		Yes	5.25 V	96	CMOS			5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No		e0				220 °C (428 °F)	24.2316 mm	No	52
EPM240ZM68I6N	Altera	Flash PLD		Ball	68	BGA	Rectangular	Plastic/Epoxy	7.9 ns		Yes	1.89 V	192	CMOS			1.8	1.5/3.3,1.8 V	Grid Array	BGA68,9X9,20	Programmable Logic Devices	Yes	Macrocell	1.71 V	.5 mm		0 Dedicated Inputs	0		Tin Silver Copper	Bottom	R-PBGA-B68				No	It can also operate at 3.3 V	e1						Yes
EPM5128AGI68-12	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	20 ns		No	5.5 V		CMOS			5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.953 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz				27.94 mm		52
EPM5128AJI68-15	Altera	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		83.3 MHz				24.13 mm		52
5962-8946801XC	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No		128	CMOS	MIL-STD-883		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Gold	Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e4	33.3 MHz			220 °C (428 °F)	27.94 mm	No	52
EPM5128AJI68-20	Altera	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns		Yes	5.5 V		CMOS			5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz				24.13 mm		52
5962-8946801XX	Altera	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns		No		128	CMOS	MIL-STD-883		5		Grid Array, Window				Macrocell		2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		33.3 MHz				27.94 mm		52

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.