68 Programmable Logic Devices (PLD) 419

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Length	JTAG Boundary Scan Test	No. of I/O Lines
PML2552-35A-T	NXP Semiconductors	OT PLD	Commercial Extended	J Bend	68	QCCJ	Square	Plastic/Epoxy		Yes	5.25 V		CMOS		5		Chip Carrier				Mixed	4.75 V	1.27 mm	75 °C (167 °F)	9 Dedicated Inputs, 24 I/O	9	0 °C (32 °F)		Quad	S-PQCC-J68		4.57 mm	24.23 mm	No			50 MHz	24.23 mm		24
PZ3064-12A68-T	NXP Semiconductors	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	14.5 ns	Yes	3.63 V		CMOS		3.3		Chip Carrier				Macrocell	2.97 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 48 I/O	2	0 °C (32 °F)		Quad	S-PQCC-J68		4.57 mm	24.2316 mm	No			67 MHz	24.2316 mm		48
PHD48N22-7A	NXP Semiconductors	OT PLD	Commercial Extended	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns	Yes	5.25 V		TTL		5		Chip Carrier				Combinatorial	4.75 V	1.27 mm	75 °C (167 °F)	36 Dedicated Inputs, 12 I/O	36	0 °C (32 °F)		Quad	S-PQCC-J68		4.57 mm	24.23 mm	No	High Speed Decoder			24.23 mm		12
PZ5064I10A68	NXP Semiconductors	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	12.5 ns	Yes	5.5 V		CMOS		5		Chip Carrier				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 48 I/O	2	-40 °C (-40 °F)		Quad	S-PQCC-J68		4.57 mm	24.2316 mm	No			77 MHz	24.2316 mm		48
PML2552-50KA-T	NXP Semiconductors	OT PLD	Commercial Extended	J Bend	68	QCCJ	Square	Ceramic, Metal-Sealed Cofired		Yes	5.25 V		CMOS		5		Chip Carrier				Mixed	4.75 V	1.27 mm	75 °C (167 °F)	9 Dedicated Inputs, 24 I/O	9	0 °C (32 °F)		Quad	S-CQCC-J68		4.83 mm	24.065 mm	No			35 MHz	24.065 mm		24
PZ3064I12A68	NXP Semiconductors	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	14.5 ns	Yes	3.63 V		CMOS		3.3		Chip Carrier				Macrocell	2.97 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 48 I/O	2	-40 °C (-40 °F)		Quad	S-PQCC-J68		4.57 mm	24.2316 mm	No			67 MHz	24.2316 mm		48
PZ5064-10A68	NXP Semiconductors	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	12.5 ns	Yes	5.25 V		CMOS		5		Chip Carrier				Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 48 I/O	2	0 °C (32 °F)		Quad	S-PQCC-J68		4.57 mm	24.2316 mm	No			77 MHz	24.2316 mm		48
PZ5064I12A68	NXP Semiconductors	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	14.5 ns	Yes	5.5 V		CMOS		5		Chip Carrier				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 48 I/O	2	-40 °C (-40 °F)		Quad	S-PQCC-J68		4.57 mm	24.2316 mm	No			67 MHz	24.2316 mm		48
5962-8946804XA	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	42 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz	27.9527 mm		52
5962-8946803XA	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	51 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	33.3 MHz	27.9527 mm		52
5962-8946804XX	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	42 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz	27.9527 mm		52
5962-8946805XA	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	50 MHz	27.9527 mm		52
5962-8946805XX	Infineon Technologies	UV PLD	Military	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	33 ns	No	5.5 V		CMOS		5		Grid Array, Window				Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68		5.08 mm	27.9527 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		50 MHz	27.9527 mm		52
5962-8946803XX	Infineon Technologies	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	51 ns	No	5.5 V		CMOS	MIL-STD-883	5		Grid Array				Macrocell	4.5 V		125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Perpendicular	S-CPGA-P68				No						52
XCR5064-10PC68C	Xilinx	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns	Yes	5.25 V	64	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 48 I/O	2	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No			77 MHz	24.2316 mm	No	48
XC7354-10WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	22 ns	Yes	5.5 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 42 I/O	8	-40 °C (-40 °F)	Tin Lead	Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	76.9 MHz	24.13 mm	No	42
XC7272A-16WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns	Yes	5.25 V	72	CMOS		5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 38 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		55 MHz	24.13 mm	No	38
XC7372-7WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	18.5 ns	Yes	5.25 V	72	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		95.2 MHz	24.13 mm	No	25
XC7272-30PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	48 ns	Yes		72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0			No
XC7372-12WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	28 ns	Yes	5.25 V	72	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz	24.13 mm	No	25
XC7354-7WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	16.5 ns	Yes	5.25 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		95.2 MHz	24.13 mm	No	42
XC7372-10WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	23 ns	Yes	5.25 V	72	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		71.4 MHz	24.13 mm	No	25
XC7354-15WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.25 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		55.6 MHz	24.13 mm	No	42
XCR5064-10PC68I	Xilinx	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns	Yes	5.5 V	64	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 48 I/O	2	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No			77 MHz	24.2316 mm	No	48
XC7272-25PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns	Yes		72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0			No
XC7354-15WC68M	Xilinx	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	8 Dedicated Inputs, 42 I/O	8	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	55.6 MHz	24.13 mm	No	42
XC7354-7PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	16.5 ns	Yes	5.25 V	54	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	95.2 MHz	24.2316 mm	No	42
XCR5064-12PC68I	Xilinx	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	12 ns	Yes	5.5 V	64	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 48 I/O	2	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No			67 MHz	24.2316 mm	No	48
XC7272A-16WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns	Yes	5.5 V	72	CMOS		5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 38 I/O	8	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		55 MHz	24.13 mm	No	38
XC7272A-16PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	25 ns	Yes	5.5 V	72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 38 I/O	8	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		55 MHz	24.2316 mm	No	38
XC7272-25PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns	Yes		72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0			No
XC7272A-25PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns	Yes	5.5 V	72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 38 I/O	8	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz	24.2316 mm	No	38
XC7354-12PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	27 ns	Yes	5.25 V	54	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		66.7 MHz	24.2316 mm	No	42
XC7372-12WC68M	Xilinx	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	28 ns	Yes	5.5 V	72	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	10 Dedicated Inputs, 25 I/O	10	-55 °C (-67 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz	24.13 mm	No	25
XC7372-12PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns	Yes	5.25 V	72	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz	24.2316 mm	No	25
XC7272-30WC68I	Xilinx	UV PLD	Industrial	J Bend	68	QCCJ	Square	Ceramic	48 ns	Yes		72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)		Quad	S-XQCC-J68				No					No
XC7372-15PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	33 ns	Yes	5.25 V	72	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz	24.2316 mm	No	25
XC7354-10WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	22 ns	Yes	5.25 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	76.9 MHz	24.13 mm	No	42
XC7354-15WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 42 I/O	8	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		55.6 MHz	24.13 mm	No	42
XC7272A-25WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	40 ns	Yes	5.5 V	72	CMOS		5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 38 I/O	8	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz	24.13 mm	No	38
XC7272-30WC68C	Xilinx	UV PLD	Commercial	J Bend	68	QCCJ	Square	Ceramic	48 ns	Yes		72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)		Quad	S-XQCC-J68				No					No
XC7272A-20WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V	72	CMOS		5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 38 I/O	8	-40 °C (-40 °F)	Tin Lead	Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells	e0	50 MHz	24.13 mm	No	38
XC7354-10PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	22 ns	Yes	5.5 V	54	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 42 I/O	8	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	76.9 MHz	24.2316 mm	No	42
XC7272A-25WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	40 ns	Yes	5.25 V	72	CMOS		5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 38 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz	24.13 mm	No	38
XC7272-25WC68C	Xilinx	UV PLD	Commercial	J Bend	68	QCCJ	Square	Ceramic	40 ns	Yes		72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)		Quad	S-XQCC-J68				No					No
XC7372-15WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns	Yes	5.25 V	72	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz	24.13 mm	No	25
XC7354-12WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	27 ns	Yes	5.25 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		66.7 MHz	24.13 mm	No	42
XC7354-12WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	27 ns	Yes	5.5 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 42 I/O	8	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		66.7 MHz	24.13 mm	No	42

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.