68 Programmable Logic Devices (PLD) 419

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
XC7354-15PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	32 ns	Yes	5.5 V	54	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 42 I/O	8	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	55.6 MHz		24.2316 mm	No	42
XC7272A-25PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns	Yes	5.25 V	72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 38 I/O	8	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells	e0	40 MHz		24.2316 mm	No	38
XC7272-30PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	48 ns	Yes		72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				No
XC7372-15WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns	Yes	5.5 V	72	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	10 Dedicated Inputs, 25 I/O	10	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz		24.13 mm	No	25
XCR3064-15PC68I	Xilinx	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns	Yes	3.6 V	64	CMOS		3.3	3.3 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	2.97 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 48 I/O	2	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No			58 MHz		24.2316 mm	No	48
XC7372-15WC68M	Xilinx	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns	Yes	5.5 V	72	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	10 Dedicated Inputs, 25 I/O	10	-55 °C (-67 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz		24.13 mm	No	25
XC7354-12WC68M	Xilinx	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	27 ns	Yes	5.5 V	54	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	8 Dedicated Inputs, 42 I/O	8	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	66.7 MHz		24.13 mm	No	42
XC7272A-20WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.25 V	72	CMOS		5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 38 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		50 MHz		24.13 mm	No	38
XC7272A-16PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	25 ns	Yes	5.25 V	72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 38 I/O	8	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		55 MHz		24.2316 mm	No	38
XC7354-10PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	22 ns	Yes	5.25 V	54	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	76.9 MHz		24.2316 mm	No	42
XC7354-12PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	27 ns	Yes	5.5 V	54	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 42 I/O	8	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		66.7 MHz		24.2316 mm	No	42
XC7272A-20PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	32 ns	Yes	5.5 V	72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 38 I/O	8	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells	e0	50 MHz		24.2316 mm	No	38
XCR3064-10PC68C	Xilinx	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns	Yes	3.6 V	64	CMOS		3.3	3.3 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	2.97 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 48 I/O	2	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No			80 MHz		24.2316 mm	No	48
XC7372-15PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	33 ns	Yes	5.5 V	72	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	10 Dedicated Inputs, 25 I/O	10	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz		24.2316 mm	No	25
XC7372-7PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	18.5 ns	Yes	5.25 V	72	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		95.2 MHz		24.2316 mm	No	25
XCR3064-12PC68I	Xilinx	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	12 ns	Yes	3.6 V	64	CMOS		3.3	3.3 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	2.97 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 48 I/O	2	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No			67 MHz		24.2316 mm	No	48
XCR3064-12PC68C	Xilinx	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	12 ns	Yes	3.6 V	64	CMOS		3.3	3.3 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	2.97 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 48 I/O	2	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No			67 MHz		24.2316 mm	No	48
XC7372-12PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns	Yes	5.5 V	72	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	10 Dedicated Inputs, 25 I/O	10	-40 °C (-40 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz		24.2316 mm	No	25
XCR5064-7PC68C	Xilinx	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	7.5 ns	Yes	5.25 V	64	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 48 I/O	2	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No			105 MHz		24.2316 mm	No	48
XC7372-10PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	23 ns	Yes	5.5 V	72	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	10 Dedicated Inputs, 25 I/O	10	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops	e0	71.4 MHz		24.2316 mm	No	25
XC7272A-20PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	32 ns	Yes	5.25 V	72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 38 I/O	8	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		50 MHz		24.2316 mm	No	38
XC7372-7PC68I	Xilinx	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	7.5 ns	Yes		72	CMOS			3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0				No
XC7372-12WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	28 ns	Yes	5.5 V	72	CMOS		5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	10 Dedicated Inputs, 25 I/O	10	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz		24.13 mm	No	25
XC7372-10PC68C	Xilinx	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	23 ns	Yes	5.25 V	72	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-PQCC-J68	1	5.08 mm	24.2316 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		71.4 MHz		24.2316 mm	No	25
XC7272-25WC68I	Xilinx	UV PLD	Industrial	J Bend	68	QCCJ	Square	Ceramic	40 ns	Yes		72	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)		Quad	S-XQCC-J68				No						No
EP1810LI-40	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic	45 ns	Yes		48	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0		220 °C (428 °F)		No
5M160ZM68C4N	Altera	Flash PLD	Other	Ball	68	TFBGA	Square	Plastic/Epoxy	7.9 ns	Yes	1.89 V	128	CMOS		1.8	1.2/3.3,1.8 V	Grid Array, Thin Profile, Fine Pitch	BGA68,9X9,20	Programmable Logic Devices	Yes	Macrocell	1.71 V	.5 mm	85 °C (185 °F)	52 I/O		0 °C (32 °F)	Tin Silver Copper	Bottom	S-PBGA-B68		1.2 mm	5 mm	No		e1	184.1 MHz		5 mm	Yes	52
EPM7064SLI68-15	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns	Yes	5.5 V	64	CMOS		5	3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	0 Dedicated Inputs, 48 I/O	0	-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.23 mm	No	Configurable I/O operation with 3.3 V or 5 V	e0	76.9 MHz	220 °C (428 °F)	24.23 mm	No	48
EP1810LI68-35	Altera	OT PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns	Yes	5.5 V		CMOS		5		Chip Carrier				Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	48 Macrocells; Shared Input/Clock		40 MHz		24.2316 mm		48
EP1800JI-3	Altera	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	80 ns	Yes	5.5 V	48	CMOS		5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 48 I/O	12	-40 °C (-40 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	48 Macrocells	e0	18.5 MHz	220 °C (428 °F)	24.13 mm	No	48
EPM7096LC68-15H	Altera	EE PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	15 ns	Yes	5.25 V		CMOS		5		Chip Carrier				Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	0 Dedicated Inputs, 52 I/O	0	0 °C (32 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No			100 MHz		24.2316 mm		52
EP1810LC68-25	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns	Yes	5.25 V	48	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	48 Macrocells; Shared Input/Clock	e0	50 MHz	220 °C (428 °F)	24.2316 mm	No	48
EPM5128ALM68-20	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Plastic/Epoxy	33 ns	Yes	5.5 V		CMOS		5		Chip Carrier				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz		24.2316 mm		52
5M240ZM68A5N	Altera	Flash PLD	Industrial	Ball	68	FBGA	Square	Plastic/Epoxy	17.7 ns	Yes		192	CMOS			1.8,1.2/3.3 V	Grid Array, Fine Pitch	BGA68,9X9,20	Programmable Logic Devices	Yes			.5 mm	105 °C (221 °F)			-40 °C (-40 °F)		Bottom	S-PBGA-B68				No						Yes
5962-01-429-6233	Altera	OT PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	50 ns	No		48	CMOS	38535Q/M;38534H;883B	5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)		Perpendicular	S-XPGA-P68				No						No
5962-01-324-9620	Altera	UV PLD	Military	Pin/Peg	68	PGA	Square	Ceramic	75 ns	No		48	CMOS	38535Q/M;38534H;883B	5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No			2.54 mm	125 °C (257 °F)			-55 °C (-67 °F)		Perpendicular	S-XPGA-P68				No						No
EPM5128JM68	Altera	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns	Yes	5.5 V		CMOS		5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	7 Dedicated Inputs, 52 I/O	7	-55 °C (-67 °F)		Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms		33.3 MHz		24.13 mm		52
MP1810LC-35	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	40 ns	Yes		48	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0		220 °C (428 °F)		No
EPM5128ALC68-12	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	20 ns	Yes	5.25 V		CMOS		5		Chip Carrier				Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		111.1 MHz		24.2316 mm		52
MP1810LC-25	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	28 ns	Yes		48	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	70 °C (158 °F)			0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0		220 °C (428 °F)		No
EP1810GC68-45	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	50 ns	No	5.25 V		CMOS		5		Grid Array, Window				Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock		33.3 MHz		27.94 mm		48
EP1830JM-30	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Ceramic	34 ns	Yes		48	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-XQCC-J68				No		e0		220 °C (428 °F)		No
EPM7064SLI68-10	Altera	EE PLD	Industrial	J Bend	68	QCCJ	Square	Plastic/Epoxy	10 ns	Yes		64	CMOS			3.3/5,5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	Yes			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)	Tin Lead	Quad	S-PQCC-J68				No		e0		220 °C (428 °F)		No
EPM5128ALC68-20	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	33 ns	Yes	5.25 V		CMOS		5		Chip Carrier				Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)		Quad	S-PQCC-J68		5.08 mm	24.2316 mm	No	Labs interconnected by PIA; 8 Labs; 1 External Clock		66.7 MHz	220 °C (428 °F)	24.2316 mm		52
EP1800LC-1	Altera	OT PLD	Commercial	J Bend	68	QCCJ	Square	Plastic/Epoxy	90 ns	Yes	5.25 V	48	CMOS		5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-PQCC-J68			24.2316 mm	No	48 Macrocells	e0	25 MHz	220 °C (428 °F)	24.2316 mm	No	48
EP1810GC68-35	Altera	UV PLD	Commercial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.25 V	48	CMOS		5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 48 I/O	12	0 °C (32 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	48 Macrocells; Shared Input/Clock	e0	40 MHz	220 °C (428 °F)	27.94 mm	No	48
EP1810JM883B	Altera	OT PLD	Military	J Bend	68	QCCJ	Square	Ceramic	50 ns	Yes		48	CMOS	38535Q/M;38534H;883B	5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No			1.27 mm	125 °C (257 °F)			-55 °C (-67 °F)	Tin Lead	Quad	S-XQCC-J68				No		e0		220 °C (428 °F)		No
5M240ZM68I5	Altera	Flash PLD	Industrial	Ball	68	TFBGA	Square	Plastic/Epoxy	14 ns	Yes	1.89 V	192	CMOS		1.8	1.8,1.2/3.3 V	Grid Array, Thin Profile, Fine Pitch	BGA68,9X9,20	Programmable Logic Devices	Yes	Macrocell	1.71 V	.5 mm	100 °C (212 °F)	52 I/O		-40 °C (-40 °F)	Tin Lead	Bottom	S-PBGA-B68		1.2 mm	5 mm	No		e0	118.3 MHz		5 mm	Yes	52

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.