UV PLD Programmable Logic Devices (PLD) 725

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Part RoHS Manufacturer Programmable IC Type Grading Of Temperature Form Of Terminal No. of Terminals Package Code Package Shape Package Body Material Propagation Delay No. of Logic Cells Surface Mount Maximum Supply Voltage No. of Macro Cells Technology Used Screening Level No. of Inputs Architecture Nominal Supply Voltage (V) Packing Method Power Supplies (V) Package Style (Meter) Package Equivalence Code Sub-Category In-System Programmable Output Function Minimum Supply Voltage No. of Product Terms Pitch Of Terminal Maximum Operating Temperature Organization No. of Dedicated Inputs Minimum Operating Temperature Finishing Of Terminal Used Position Of Terminal JESD-30 Code Moisture Sensitivity Level (MSL) Maximum Seated Height Width Qualification Additional Features JESD-609 Code Maximum Clock Frequency Maximum Time At Peak Reflow Temperature (s) No. of Outputs Peak Reflow Temperature (C) Length JTAG Boundary Scan Test No. of I/O Lines

EP910DC-30

Texas Instruments

UV PLD

Commercial

Through-Hole

40

DIP

Rectangular

Ceramic, Metal-Sealed Cofired

33 ns

No

5.25 V

CMOS

36

PAL-TYPE

5

5 V

In-Line

DIP40,.6

Programmable Logic Devices

Macrocell

4.75 V

240

2.54 mm

70 °C (158 °F)

12 Dedicated Inputs, 24 I/O

12

0 °C (32 °F)

Dual

R-CDIP-T40

No

24 Macrocell; Configurable I/O

33.3 MHz

24

24

TICPAL22V10MJL

Texas Instruments

UV PLD

Military

Through-Hole

24

DIP

Rectangular

Ceramic, Glass-Sealed

No

5.5 V

CMOS

22

PAL-TYPE

5

5 V

In-Line

DIP24(UNSPEC)

Programmable Logic Devices

Macrocell

4.5 V

132

125 °C (257 °F)

11 Dedicated Inputs, 10 I/O

11

-55 °C (-67 °F)

Dual

R-GDIP-T24

No

Shared Input/Clock

10

10

TICPAL18V8-30MJL

Texas Instruments

UV PLD

Military

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

30 ns

No

5.5 V

CMOS

18

PAL-TYPE

5

5 V

In-Line

DIP20,.3

Programmable Logic Devices

Macrocell

4.5 V

74

2.54 mm

125 °C (257 °F)

9 Dedicated Inputs, 8 I/O

9

-55 °C (-67 °F)

Dual

R-GDIP-T20

No

PAL with Macrocells; 8 Macrocells; 1 External Clock; Shared Input/Clock

35 MHz

8

8

EP910DI-45

Texas Instruments

UV PLD

Industrial

Through-Hole

40

DIP

Rectangular

Ceramic, Metal-Sealed Cofired

45 ns

No

5.5 V

CMOS

36

PAL-TYPE

5

5 V

In-Line

DIP40,.6

Programmable Logic Devices

Macrocell

4.5 V

240

2.54 mm

85 °C (185 °F)

12 Dedicated Inputs, 24 I/O

12

-40 °C (-40 °F)

Dual

R-CDIP-T40

No

22.2 MHz

24

24

TICPAL18V8-25CJL

Texas Instruments

UV PLD

Commercial Extended

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

25 ns

No

5.25 V

CMOS

18

PAL-TYPE

5

5 V

In-Line

DIP20,.3

Programmable Logic Devices

Macrocell

4.75 V

74

2.54 mm

75 °C (167 °F)

9 Dedicated Inputs, 8 I/O

9

0 °C (32 °F)

Dual

R-GDIP-T20

No

PAL with Macrocells; 8 Macrocells; 1 External Clock; Shared Input/Clock

35 MHz

8

8

TICPAL22V10Z-35CJT

Texas Instruments

UV PLD

Commercial Extended

Through-Hole

24

DIP

Rectangular

Ceramic, Glass-Sealed

40 ns

No

5.25 V

CMOS

5

In-Line

Macrocell

4.75 V

75 °C (167 °F)

11 Dedicated Inputs, 10 I/O

11

0 °C (32 °F)

Dual

R-GDIP-T24

No

Shared Input/Clock

20 MHz

10

EP910JC-40

Texas Instruments

UV PLD

Commercial

J Bend

44

QCCJ

Square

Ceramic, Metal-Sealed Cofired

40 ns

Yes

5.25 V

CMOS

36

PAL-TYPE

5

5 V

Chip Carrier

LDCC44,.7SQ

Programmable Logic Devices

Macrocell

4.75 V

240

1.27 mm

70 °C (158 °F)

12 Dedicated Inputs, 24 I/O

12

0 °C (32 °F)

Quad

S-CQCC-J44

No

25 MHz

24

24

EP610JI-40

Texas Instruments

UV PLD

Industrial

J Bend

28

QCCJ

Square

Ceramic, Metal-Sealed Cofired

40 ns

Yes

5.5 V

CMOS

20

PAL-TYPE

5

5 V

Chip Carrier

LDCC28,.5SQ

Programmable Logic Devices

Macrocell

4.5 V

160

1.27 mm

85 °C (185 °F)

4 Dedicated Inputs, 16 I/O

4

-40 °C (-40 °F)

Quad

S-CQCC-J28

No

Zero Standby Function; 16 Macrocells With Configurable I/O

16

16

TICPAL16L8-55CJL

Texas Instruments

UV PLD

Commercial Extended

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

55 ns

No

5.25 V

CMOS

16

PAL-TYPE

5

5 V

In-Line

DIP20,.3

Programmable Logic Devices

Combinatorial

4.75 V

64

2.54 mm

75 °C (167 °F)

10 Dedicated Inputs, 6 I/O

10

0 °C (32 °F)

Dual

R-GDIP-T20

No

8

6

EP910DC-35

Texas Instruments

UV PLD

Commercial

Through-Hole

40

DIP

Rectangular

Ceramic, Metal-Sealed Cofired

35 ns

No

5.25 V

CMOS

36

PAL-TYPE

5

5 V

In-Line

DIP40,.6

Programmable Logic Devices

Macrocell

4.75 V

240

2.54 mm

70 °C (158 °F)

12 Dedicated Inputs, 24 I/O

12

0 °C (32 °F)

Dual

R-CDIP-T40

No

37 MHz

24

24

EP1810JI-45

Texas Instruments

UV PLD

Industrial

J Bend

68

QCCJ

Square

Ceramic, Metal-Sealed Cofired

50 ns

Yes

5.5 V

48

CMOS

5

5 V

Chip Carrier

LDCC68,1.0SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

12 Dedicated Inputs, 48 I/O

12

-40 °C (-40 °F)

Quad

S-CQCC-J68

No

48 Macrocell; Configurable I/O

33.3 MHz

No

48

EP1810JC-35

Texas Instruments

UV PLD

Commercial

J Bend

68

QCCJ

Square

Ceramic, Metal-Sealed Cofired

40 ns

Yes

5.25 V

48

CMOS

5

5 V

Chip Carrier

LDCC68,1.0SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

12 Dedicated Inputs, 48 I/O

12

0 °C (32 °F)

Quad

S-CQCC-J68

No

48 Macrocell; Configurable I/O

40 MHz

No

48

TICPAL22V10Z-25CJT

Texas Instruments

UV PLD

Commercial Extended

Through-Hole

24

DIP

Rectangular

Ceramic, Glass-Sealed

30 ns

No

5.25 V

CMOS

5

In-Line

Macrocell

4.75 V

75 °C (167 °F)

11 Dedicated Inputs, 10 I/O

11

0 °C (32 °F)

Dual

R-GDIP-T24

No

Shared Input/Clock

28.5 MHz

10

TICPAL16R4-55CJL

Texas Instruments

UV PLD

Commercial Extended

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

55 ns

No

5.25 V

CMOS

16

PAL-TYPE

5

5 V

In-Line

DIP20,.3

Programmable Logic Devices

Mixed

4.75 V

64

2.54 mm

75 °C (167 °F)

8 Dedicated Inputs, 4 I/O

8

0 °C (32 °F)

Dual

R-GDIP-T20

No

Register Preload

16 MHz

4

4

P3C18V8Z40FA

NXP Semiconductors

UV PLD

Commercial Extended

Through-Hole

20

DIP

Rectangular

Ceramic, Metal-Sealed Cofired

40 ns

No

3.6 V

CMOS

3.3

In-Line

Macrocell

3 V

2.54 mm

75 °C (167 °F)

8 Dedicated Inputs, 8 I/O

8

0 °C (32 °F)

Dual

R-CDIP-T20

5.08 mm

7.62 mm

No

Programmable Output Polarity

22 MHz

24.305 mm

8

P3C18V8ZIAFA

NXP Semiconductors

UV PLD

Industrial

Through-Hole

20

DIP

Rectangular

Ceramic, Metal-Sealed Cofired

45 ns

No

3.6 V

CMOS

3.3

In-Line

Macrocell

3 V

2.54 mm

85 °C (185 °F)

8 Dedicated Inputs, 8 I/O

8

-40 °C (-40 °F)

Dual

R-CDIP-T20

5.08 mm

7.62 mm

No

Programmable Output Polarity

18 MHz

24.305 mm

8

PLC18V8Z25FA

NXP Semiconductors

UV PLD

Commercial Extended

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

25 ns

No

5.25 V

CMOS

5

In-Line

Macrocell

4.75 V

2.54 mm

75 °C (167 °F)

8 Dedicated Inputs, 8 I/O

8

0 °C (32 °F)

Dual

R-GDIP-T20

5.08 mm

7.62 mm

No

8 Macrocells; 1 External Clock; Shared Input/Clock; Register Preload; Power-Up Reset

30 MHz

24.305 mm

8

PLC18V8ZIFA

NXP Semiconductors

UV PLD

Industrial

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

40 ns

No

5.5 V

CMOS

5

In-Line

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

8 Dedicated Inputs, 8 I/O

8

-40 °C (-40 °F)

Dual

R-GDIP-T20

5.08 mm

7.62 mm

No

8 Macrocells; 1 External Clock; Shared Input/Clock; Register Preload; Power-Up Reset

18 MHz

24.305 mm

8

P3C18V8ZIFA

NXP Semiconductors

UV PLD

Industrial

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

50 ns

No

3.6 V

CMOS

3.3

In-Line

Macrocell

2.7 V

2.54 mm

85 °C (185 °F)

8 Dedicated Inputs, 8 I/O

8

-40 °C (-40 °F)

Dual

R-GDIP-T20

5.08 mm

7.62 mm

No

8 Macrocells; Register Preload; Power-Up Reset; 1 External Clock; Shared Input/Clock

17 MHz

24.305 mm

8

PLC415-16FA

NXP Semiconductors

UV PLD

Commercial Extended

Through-Hole

28

DIP

Rectangular

Ceramic, Glass-Sealed

40 ns

No

5.25 V

CMOS

5

In-Line

Registered

4.75 V

75 °C (167 °F)

15 Dedicated Inputs, 0 I/O

15

0 °C (32 °F)

Dual

R-GDIP-T28

No

Programmable Logic Sequencer; 2 External Clocks; Shared Input/Clock

13.3 MHz

0

PLC18V8Z/BRA

NXP Semiconductors

UV PLD

Military

Through-Hole

20

WDIP

Rectangular

Ceramic, Glass-Sealed

30 ns

No

5.5 V

CMOS

5

In-Line, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

8 Dedicated Inputs, 8 I/O

8

-55 °C (-67 °F)

Dual

R-GDIP-T20

5.08 mm

7.62 mm

No

25 MHz

8

PLC18V8ZIAFA

NXP Semiconductors

UV PLD

Industrial

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

25 ns

No

5.5 V

CMOS

5

In-Line

Macrocell

4.5 V

2.54 mm

85 °C (185 °F)

8 Dedicated Inputs, 8 I/O

8

-40 °C (-40 °F)

Dual

R-GDIP-T20

5.08 mm

7.62 mm

No

8 Macrocells; 1 External Clock; Shared Input/Clock; Register Preload; Power-Up Reset

30 MHz

24.305 mm

8

PLC42VA12IFA

NXP Semiconductors

UV PLD

Industrial

Through-Hole

24

DIP

Rectangular

Ceramic, Glass-Sealed

55 ns

No

5.5 V

CMOS

5

In-Line

Macrocell

4.5 V

85 °C (185 °F)

8 Dedicated Inputs, 12 I/O

8

-40 °C (-40 °F)

Dual

R-GDIP-T24

No

Programmable Multi-Function Pld; Register Preload; Shared Input/Clock

14.9 MHz

12

PLC18V8Z35FA

NXP Semiconductors

UV PLD

Commercial Extended

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

35 ns

No

5.25 V

CMOS

5

In-Line

Macrocell

4.75 V

2.54 mm

75 °C (167 °F)

8 Dedicated Inputs, 8 I/O

8

0 °C (32 °F)

Dual

R-GDIP-T20

5.08 mm

7.62 mm

No

8 Macrocells; 1 External Clock; Shared Input/Clock; Register Preload; Power-Up Reset

21 MHz

24.305 mm

8

P3C18V8Z35FA

NXP Semiconductors

UV PLD

Commercial Extended

Through-Hole

20

DIP

Rectangular

Ceramic, Glass-Sealed

45 ns

No

3.6 V

CMOS

3.3

In-Line

Macrocell

2.7 V

2.54 mm

75 °C (167 °F)

8 Dedicated Inputs, 8 I/O

8

0 °C (32 °F)

Dual

R-GDIP-T20

5.08 mm

7.62 mm

No

8 Macrocells; Register Preload; Power-Up Reset; 1 External Clock; Shared Input/Clock

21 MHz

24.305 mm

8

PLC42VA12FA

NXP Semiconductors

UV PLD

Commercial Extended

Through-Hole

24

DIP

Rectangular

Ceramic, Glass-Sealed

55 ns

No

5.25 V

CMOS

42

PLS-TYPE

5

5 V

In-Line

DIP24,.3

Programmable Logic Devices

Macrocell

4.75 V

105

2.54 mm

75 °C (167 °F)

8 Dedicated Inputs, 12 I/O

8

0 °C (32 °F)

Dual

R-GDIP-T24

1

No

Programmable Multi-Function Pld; 1 External Clock; Shared Input/Clock; Register Preload

14.9 MHz

12

12

59628753906LX

Infineon Technologies

UV PLD

Military

Through-Hole

WDIP

Ceramic, Glass-Sealed

10 ns

No

5.5 V

CMOS

5

In-Line, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

11 Dedicated Inputs, 10 I/O

11

-55 °C (-67 °F)

Tin Lead

Dual

5.08 mm

7.62 mm

No

10 Macrocells; 1 External Clock; Shared Input/Clock; Variable Product Terms

e0

83 MHz

32 mm

10

5962-8946804XA

Infineon Technologies

UV PLD

Military

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

42 ns

No

5.5 V

CMOS

5

Grid Array, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

7 Dedicated Inputs, 52 I/O

7

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-CPGA-P68

5.08 mm

27.9527 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

e0

40 MHz

27.9527 mm

52

5962-8946803XA

Infineon Technologies

UV PLD

Military

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

51 ns

No

5.5 V

CMOS

5

Grid Array, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

7 Dedicated Inputs, 52 I/O

7

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-CPGA-P68

5.08 mm

27.9527 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

e0

33.3 MHz

27.9527 mm

52

5962-8946804XX

Infineon Technologies

UV PLD

Military

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

42 ns

No

5.5 V

CMOS

5

Grid Array, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

7 Dedicated Inputs, 52 I/O

7

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-CPGA-P68

5.08 mm

27.9527 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

e0

40 MHz

27.9527 mm

52

5962-8946805XA

Infineon Technologies

UV PLD

Military

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

33 ns

No

5.5 V

CMOS

5

Grid Array, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

7 Dedicated Inputs, 52 I/O

7

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-CPGA-P68

5.08 mm

27.9527 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

e0

50 MHz

27.9527 mm

52

5962-8946805XX

Infineon Technologies

UV PLD

Military

Pin/Peg

68

WPGA

Square

Ceramic, Metal-Sealed Cofired

33 ns

No

5.5 V

CMOS

5

Grid Array, Window

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

7 Dedicated Inputs, 52 I/O

7

-55 °C (-67 °F)

Perpendicular

S-CPGA-P68

5.08 mm

27.9527 mm

No

Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock

50 MHz

27.9527 mm

52

5962-8946803XX

Infineon Technologies

UV PLD

Military

Pin/Peg

68

PGA

Square

Ceramic, Metal-Sealed Cofired

51 ns

No

5.5 V

CMOS

MIL-STD-883

5

Grid Array

Macrocell

4.5 V

125 °C (257 °F)

7 Dedicated Inputs, 52 I/O

7

-55 °C (-67 °F)

Perpendicular

S-CPGA-P68

No

52

XC73108-20WC84M

Xilinx

UV PLD

Military

J Bend

84

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

45 ns

Yes

5.5 V

108

CMOS

5

3.3/5,5 V

Chip Carrier, Window

LDCC84,1.2SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

125 °C (257 °F)

12 Dedicated Inputs, 37 I/O

12

-55 °C (-67 °F)

Quad

S-CQCC-J84

1

4.826 mm

29.21 mm

No

108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops

35.7 MHz

29.21 mm

No

37

XC7336-7WC44C

Xilinx

UV PLD

Commercial

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

12 ns

Yes

5.25 V

36

CMOS

5

3.3/5,5 V

Chip Carrier, Window

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

2 Dedicated Inputs, 32 I/O

2

0 °C (32 °F)

Tin Lead

Quad

S-CQCC-J44

1

4.826 mm

16.51 mm

No

36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops

e0

125 MHz

16.51 mm

No

32

XC7236-25WC44I

Xilinx

UV PLD

Industrial

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

40 ns

Yes

5.5 V

36

CMOS

5

5 V

Chip Carrier, Window

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

2 Dedicated Inputs, 30 I/O

2

-40 °C (-40 °F)

Quad

S-CQCC-J44

4.826 mm

16.51 mm

No

36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks

33 MHz

16.51 mm

No

30

XC7236A-16WC44C

Xilinx

UV PLD

Commercial

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

25 ns

Yes

5.25 V

36

CMOS

5

3/5 V

Chip Carrier, Window

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

2 Dedicated Inputs, 30 I/O

2

0 °C (32 °F)

Quad

S-CQCC-J44

1

4.826 mm

16.51 mm

No

PAL Blocks interconnected by PIA; 36 Macrocells; Configurable I/O operation with 3.3 V or 5 V

60 MHz

16.51 mm

No

30

XC7372-15WC84C

Xilinx

UV PLD

Commercial

J Bend

84

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

33 ns

Yes

5.25 V

72

CMOS

5

3.3/5,5 V

Chip Carrier, Window

LDCC84,1.2SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

12 Dedicated Inputs, 37 I/O

12

0 °C (32 °F)

Quad

S-CQCC-J84

1

4.826 mm

29.21 mm

No

72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops

52.6 MHz

29.21 mm

No

37

XC7354-10WC68I

Xilinx

UV PLD

Industrial

J Bend

68

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

22 ns

Yes

5.5 V

54

CMOS

5

3.3/5,5 V

Chip Carrier, Window

LDCC68,1.0SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

8 Dedicated Inputs, 42 I/O

8

-40 °C (-40 °F)

Tin Lead

Quad

S-CQCC-J68

1

4.826 mm

24.13 mm

No

54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops

e0

76.9 MHz

24.13 mm

No

42

XC7354-10WC44C

Xilinx

UV PLD

Commercial

J Bend

44

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

22 ns

Yes

5.25 V

54

CMOS

5

3.3/5,5 V

Chip Carrier, Window

LDCC44,.7SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

8 Dedicated Inputs, 25 I/O

8

0 °C (32 °F)

Tin Lead

Quad

S-CQCC-J44

1

4.826 mm

16.51 mm

No

54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 108 Flip Flops

e0

76.9 MHz

16.51 mm

No

25

XC73144-10PG184C

Xilinx

UV PLD

Commercial

Pin/Peg

184

PGA

Square

Ceramic, Metal-Sealed Cofired

No

CMOS

5

Grid Array

Macrocell

70 °C (158 °F)

0 °C (32 °F)

Perpendicular

S-CPGA-P184

No

PAL Blocks interconnected by PIA; 144 Macrocells; Configurable I/O operation with 3.3 V or 5 V

XC7372-15WC84I

Xilinx

UV PLD

Industrial

J Bend

84

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

33 ns

Yes

5.5 V

72

CMOS

5

3.3/5,5 V

Chip Carrier, Window

LDCC84,1.2SQ

Programmable Logic Devices

No

Macrocell

4.5 V

1.27 mm

85 °C (185 °F)

12 Dedicated Inputs, 37 I/O

12

-40 °C (-40 °F)

Quad

S-CQCC-J84

1

4.826 mm

29.21 mm

No

72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops

52.6 MHz

29.21 mm

No

37

XC7272A-16WC68C

Xilinx

UV PLD

Commercial

J Bend

68

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

25 ns

Yes

5.25 V

72

CMOS

5

5 V

Chip Carrier, Window

LDCC68,1.0SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

8 Dedicated Inputs, 38 I/O

8

0 °C (32 °F)

Quad

S-CQCC-J68

1

4.826 mm

24.13 mm

No

PAL Blocks interconnected by PIA; 72 Macrocells

55 MHz

24.13 mm

No

38

XC7372-7WC68C

Xilinx

UV PLD

Commercial

J Bend

68

WQCCJ

Square

Ceramic, Metal-Sealed Cofired

18.5 ns

Yes

5.25 V

72

CMOS

5

3.3/5,5 V

Chip Carrier, Window

LDCC68,1.0SQ

Programmable Logic Devices

No

Macrocell

4.75 V

1.27 mm

70 °C (158 °F)

10 Dedicated Inputs, 25 I/O

10

0 °C (32 °F)

Quad

S-CQCC-J68

1

4.826 mm

24.13 mm

No

72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops

95.2 MHz

24.13 mm

No

25

XC73144-10WB225C

Xilinx

UV PLD

Commercial

Ball

225

WBGA

Square

Ceramic, Metal-Sealed Cofired

25 ns

Yes

5.25 V

144

CMOS

5

3.3/5,5 V

Grid Array, Window

BGA225,15X15

Programmable Logic Devices

No

Macrocell

4.75 V

1.5 mm

70 °C (158 °F)

12 Dedicated Inputs, 120 I/O

12

0 °C (32 °F)

Bottom

S-CBGA-B225

1

No

144 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 276 Flip Flops

62.5 MHz

No

120

XC73108-15PG144M

Xilinx

UV PLD

Military

Pin/Peg

144

WPGA

Square

Ceramic, Metal-Sealed Cofired

36 ns

No

5.5 V

108

CMOS

5

3.3/5,5 V

Grid Array, Window

PGA144,15X15

Programmable Logic Devices

No

Macrocell

4.5 V

2.54 mm

125 °C (257 °F)

12 Dedicated Inputs, 78 I/O

12

-55 °C (-67 °F)

Tin Lead

Perpendicular

S-CPGA-P144

3.683 mm

39.624 mm

No

108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops

e0

45.5 MHz

39.624 mm

No

78

XC73144-10PG184M

Xilinx

UV PLD

Military

Pin/Peg

184

PGA

Square

Ceramic, Metal-Sealed Cofired

No

CMOS

5

Grid Array

Macrocell

125 °C (257 °F)

-55 °C (-67 °F)

Perpendicular

S-CPGA-P184

No

PAL Blocks interconnected by PIA; 144 Macrocells; Configurable I/O operation with 3.3 V or 5 V

XC7272-25WC84I

Xilinx

UV PLD

Industrial

J Bend

84

QCCJ

Square

Ceramic

40 ns

Yes

72

CMOS

5

5 V

Chip Carrier

LDCC84,1.2SQ

Programmable Logic Devices

No

1.27 mm

85 °C (185 °F)

-40 °C (-40 °F)

Quad

S-XQCC-J84

No

No

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.