UV PLD Programmable Logic Devices (PLD) 725

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	Length	JTAG Boundary Scan Test	No. of I/O Lines
XC7354-7WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	16.5 ns	Yes	5.25 V	54	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		95.2 MHz	24.13 mm	No	42
XC7336-15WC44C	Xilinx	UV PLD	Commercial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	23 ns	Yes	5.25 V	36	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 32 I/O	2	0 °C (32 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops		66.7 MHz	16.51 mm	No	32
XC7236-30WC44I	Xilinx	UV PLD	Industrial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	48 ns	Yes	5.5 V	36	CMOS	5	5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 30 I/O	2	-40 °C (-40 °F)		Quad	S-CQCC-J44		4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks		25 MHz	16.51 mm	No	30
XC7372-10WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	23 ns	Yes	5.25 V	72	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		71.4 MHz	24.13 mm	No	25
XC7354-15WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.25 V	54	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		55.6 MHz	24.13 mm	No	42
XC73144-15PG184I	Xilinx	UV PLD	Industrial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.5 V		CMOS	5		Grid Array				Macrocell	4.5 V		85 °C (185 °F)	0 Dedicated Inputs, 120 I/O	0	-40 °C (-40 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		45.5 MHz			120
XC73144-12PG184I	Xilinx	UV PLD	Industrial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	30 ns	No	5.5 V		CMOS	5		Grid Array				Macrocell	4.5 V		85 °C (185 °F)	0 Dedicated Inputs, 120 I/O	0	-40 °C (-40 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		55.6 MHz			120
XC73144-12PG184C	Xilinx	UV PLD	Commercial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	30 ns	No	5.25 V		CMOS	5		Grid Array				Macrocell	4.75 V		70 °C (158 °F)	0 Dedicated Inputs, 120 I/O	0	0 °C (32 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		55.6 MHz			120
XC73144-10PG184I	Xilinx	UV PLD	Industrial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired		No			CMOS	5		Grid Array				Macrocell			85 °C (185 °F)			-40 °C (-40 °F)		Perpendicular	S-CPGA-P184				No	PAL Blocks interconnected by PIA; 144 Macrocells; Configurable I/O operation with 3.3 V or 5 V
XC73108-7WB225C	Xilinx	UV PLD	Commercial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	18 ns	Yes	5.25 V	108	CMOS	5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	1.5 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Bottom	S-CBGA-B225	1			No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		83.3 MHz		No	78
XC7272A-20WC84M	Xilinx	UV PLD	Military	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V	72	CMOS	5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 42 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		50 MHz	29.21 mm	No	42
XC7336-5WC44I	Xilinx	UV PLD	Industrial	J Bend	44	QCCJ	Square	Ceramic	5 ns	Yes		36	CMOS		3.3/5,5 V	Chip Carrier	LDCC44,.7SQ	Programmable Logic Devices	No			1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)		Quad	S-XQCC-J44				No					No
XC7372-12WC84M	Xilinx	UV PLD	Military	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	28 ns	Yes	5.5 V	72	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 37 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J84		4.826 mm	29.21 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks		62.5 MHz	29.21 mm	No	37
XC73108-15WB225C	Xilinx	UV PLD	Commercial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	Yes	5.25 V	108	CMOS	5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	1.5 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Bottom	S-CBGA-B225	1			No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		45.5 MHz		No	78
XC7336-10WC44I	Xilinx	UV PLD	Industrial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	15 ns	Yes	5.5 V	36	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 32 I/O	2	-40 °C (-40 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops		100 MHz	16.51 mm	No	32
XC7372-12WC84C	Xilinx	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	28 ns	Yes	5.25 V	72	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 37 I/O	12	0 °C (32 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz	29.21 mm	No	37
XC7354-15WC68M	Xilinx	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V	54	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	8 Dedicated Inputs, 42 I/O	8	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	55.6 MHz	24.13 mm	No	42
XC7354-15WC44M	Xilinx	UV PLD	Military	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V		CMOS	5		Chip Carrier, Window				Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	0 Dedicated Inputs, 42 I/O	0	-55 °C (-67 °F)		Quad	S-CQCC-J44		4.826 mm	16.51 mm	No	Configurable I/O operation with 3.3 V or 5 V		55.6 MHz	16.51 mm		42
XC7236-25WC44C	Xilinx	UV PLD	Commercial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	40 ns	Yes	5.25 V	36	CMOS	5	5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 30 I/O	2	0 °C (32 °F)		Quad	S-CQCC-J44		4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks		33 MHz	16.51 mm	No	30
XC7336-15WC44I	Xilinx	UV PLD	Industrial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	23 ns	Yes	5.5 V	36	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 32 I/O	2	-40 °C (-40 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops		66.7 MHz	16.51 mm	No	32
XC73144-12WB225C	Xilinx	UV PLD	Commercial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	30 ns	Yes	5.25 V	144	CMOS	5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	1.5 mm	70 °C (158 °F)	12 Dedicated Inputs, 120 I/O	12	0 °C (32 °F)		Bottom	S-CBGA-B225	1			No	144 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 276 Flip Flops		55.6 MHz		No	120
XC7354-12WC44I	Xilinx	UV PLD	Industrial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	27 ns	Yes	5.5 V	54	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 25 I/O	8	-40 °C (-40 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 108 Flip Flops		66.7 MHz	16.51 mm	No	25
XC7272A-25PG84C	Xilinx	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.25 V	72	CMOS	5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 42 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz	27.94 mm	No	42
XC73108-7WC84C	Xilinx	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	18 ns	Yes	5.25 V	108	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 37 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops	e0	83.3 MHz	29.21 mm	No	37
XC73108-20PG144M	Xilinx	UV PLD	Military	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V	108	CMOS	5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 78 I/O	12	-55 °C (-67 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz	39.624 mm	No	78
XC7272-30PG84I	Xilinx	UV PLD	Industrial	Pin/Peg	84	PGA	Square	Ceramic	48 ns	No		72	CMOS	5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No			2.54 mm	85 °C (185 °F)			-40 °C (-40 °F)		Perpendicular	S-XPGA-P84				No					No
XC7372-7WC84C	Xilinx	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	18.5 ns	Yes	5.25 V	72	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 37 I/O	12	0 °C (32 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		95.2 MHz	29.21 mm	No	37
XC7372-15WC84M	Xilinx	UV PLD	Military	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns	Yes	5.5 V	72	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 37 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz	29.21 mm	No	37
XC7272A-16WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns	Yes	5.25 V	72	CMOS	5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 38 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		55 MHz	24.13 mm	No	38
XC7372-7WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	18.5 ns	Yes	5.25 V	72	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	10 Dedicated Inputs, 25 I/O	10	0 °C (32 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		95.2 MHz	24.13 mm	No	25
XC73144-10WB225C	Xilinx	UV PLD	Commercial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	Yes	5.25 V	144	CMOS	5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	1.5 mm	70 °C (158 °F)	12 Dedicated Inputs, 120 I/O	12	0 °C (32 °F)		Bottom	S-CBGA-B225	1			No	144 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 276 Flip Flops		62.5 MHz		No	120
XC73108-15PG144M	Xilinx	UV PLD	Military	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.5 V	108	CMOS	5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	125 °C (257 °F)	12 Dedicated Inputs, 78 I/O	12	-55 °C (-67 °F)	Tin Lead	Perpendicular	S-CPGA-P144		3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops	e0	45.5 MHz	39.624 mm	No	78
XC7336Q-12WC44I	Xilinx	UV PLD	Industrial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	19 ns	Yes	5.5 V	36	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 32 I/O	2	-40 °C (-40 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops		80 MHz	16.51 mm	No	32
XC7354-15WC44C	Xilinx	UV PLD	Commercial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.25 V	54	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 25 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 108 Flip Flops		55.6 MHz	16.51 mm	No	25
XC7272A-20PG84C	Xilinx	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	32 ns	No	5.25 V	72	CMOS	5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 42 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		50 MHz	27.94 mm	No	42
XC7272A-25WC84C	Xilinx	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	40 ns	Yes	5.25 V	72	CMOS	5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 42 I/O	12	0 °C (32 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz	29.21 mm	No	42
XC7272A-16WC84C	Xilinx	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns	Yes	5.25 V	72	CMOS	5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 42 I/O	12	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells	e0	55 MHz	29.21 mm	No	42
XC73108-15WC84M	Xilinx	UV PLD	Military	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	36 ns	Yes	5.5 V	108	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	12 Dedicated Inputs, 37 I/O	12	-55 °C (-67 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		45.5 MHz	29.21 mm	No	37
XC73108-12PG144C	Xilinx	UV PLD	Commercial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	30 ns	No	5.25 V	108	CMOS	5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		55.6 MHz	39.624 mm	No	78
XC7272-25PG84C	Xilinx	UV PLD	Commercial	Pin/Peg	84	PGA	Square	Ceramic	40 ns	No		72	CMOS	5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No			2.54 mm	70 °C (158 °F)			0 °C (32 °F)		Perpendicular	S-XPGA-P84				No					No
XC73108-20WB225I	Xilinx	UV PLD	Industrial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	Yes	5.5 V	108	CMOS	5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	1.5 mm	85 °C (185 °F)	12 Dedicated Inputs, 78 I/O	12	-40 °C (-40 °F)		Bottom	S-CBGA-B225	1			No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz		No	78
XC7336-12WC44C	Xilinx	UV PLD	Commercial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	19 ns	Yes	5.25 V	36	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 32 I/O	2	0 °C (32 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops		80 MHz	16.51 mm	No	32
XC7272A-25PG84I	Xilinx	UV PLD	Industrial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	40 ns	No	5.5 V	72	CMOS	5	5 V	Grid Array, Window	PGA84M,11X11	Programmable Logic Devices	No	Macrocell	4.5 V	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 42 I/O	12	-40 °C (-40 °F)		Perpendicular	S-CPGA-P84		5.207 mm	27.94 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz	27.94 mm	No	42
XC73108-12WB225I	Xilinx	UV PLD	Industrial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	30 ns	Yes	5.5 V	108	CMOS	5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.5 V	1.5 mm	85 °C (185 °F)	12 Dedicated Inputs, 78 I/O	12	-40 °C (-40 °F)		Bottom	S-CBGA-B225	1			No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		55.6 MHz		No	78
XC73108-10WB225C	Xilinx	UV PLD	Commercial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	Yes	5.25 V	108	CMOS	5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	1.5 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Bottom	S-CBGA-B225	1			No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		62.5 MHz		No	78
XC7372-12WC68M	Xilinx	UV PLD	Military	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	28 ns	Yes	5.5 V	72	CMOS	5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V	1.27 mm	125 °C (257 °F)	10 Dedicated Inputs, 25 I/O	10	-55 °C (-67 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		62.5 MHz	24.13 mm	No	25
XC7272A-20WC84C	Xilinx	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.25 V	72	CMOS	5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V	1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 42 I/O	12	0 °C (32 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		50 MHz	29.21 mm	No	42
XC73144-7WB225C	Xilinx	UV PLD	Commercial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	18 ns	Yes	5.25 V	144	CMOS	5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.75 V	1.5 mm	70 °C (158 °F)	12 Dedicated Inputs, 120 I/O	12	0 °C (32 °F)		Bottom	S-CBGA-B225	1			No	144 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 276 Flip Flops		83.3 MHz		No	120

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.