UV PLD Programmable Logic Devices (PLD) 725

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Part	Manufacturer	Programmable IC Type	Grading Of Temperature	Form Of Terminal	No. of Terminals	Package Code	Package Shape	Package Body Material	Propagation Delay	Surface Mount	Maximum Supply Voltage	No. of Macro Cells	Technology Used	Screening Level	No. of Inputs	Architecture	Nominal Supply Voltage (V)	Power Supplies (V)	Package Style (Meter)	Package Equivalence Code	Sub-Category	In-System Programmable	Output Function	Minimum Supply Voltage	No. of Product Terms	Pitch Of Terminal	Maximum Operating Temperature	Organization	No. of Dedicated Inputs	Minimum Operating Temperature	Finishing Of Terminal Used	Position Of Terminal	JESD-30 Code	Moisture Sensitivity Level (MSL)	Maximum Seated Height	Width	Qualification	Additional Features	JESD-609 Code	Maximum Clock Frequency	No. of Outputs	Peak Reflow Temperature (C)	Length	JTAG Boundary Scan Test	No. of I/O Lines
XC73108-20WC84I	Xilinx	UV PLD	Industrial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	45 ns	Yes	5.5 V	108	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 37 I/O	12	-40 °C (-40 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz			29.21 mm	No	37
XC7272-30WC68I	Xilinx	UV PLD	Industrial	J Bend	68	QCCJ	Square	Ceramic	48 ns	Yes		72	CMOS				5	5 V	Chip Carrier	LDCC68,1.0SQ	Programmable Logic Devices	No				1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)		Quad	S-XQCC-J68				No							No
XC73108-15PG144I	Xilinx	UV PLD	Industrial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.5 V	108	CMOS				5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.5 V		2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 78 I/O	12	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P144		3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops	e0	45.5 MHz			39.624 mm	No	78
XC7354-10WC68C	Xilinx	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	22 ns	Yes	5.25 V	54	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 42 I/O	8	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops	e0	76.9 MHz			24.13 mm	No	42
XC7336-15WC44M	Xilinx	UV PLD	Military	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	23 ns	Yes	5.5 V		CMOS				5		Chip Carrier, Window				Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	0 Dedicated Inputs, 32 I/O	0	-55 °C (-67 °F)		Quad	S-CQCC-J44		4.826 mm	16.51 mm	No	Configurable I/O operation with 3.3 V or 5 V; 18 Output Macrocells		41.67 MHz			16.51 mm		32
XC7272A-25WC84I	Xilinx	UV PLD	Industrial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	40 ns	Yes	5.5 V	72	CMOS				5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 42 I/O	12	-40 °C (-40 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz			29.21 mm	No	42
XC73108-20WC84C	Xilinx	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	45 ns	Yes	5.25 V	108	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 37 I/O	12	0 °C (32 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz			29.21 mm	No	37
XC73108-12WC84I	Xilinx	UV PLD	Industrial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	30 ns	Yes	5.5 V	108	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 37 I/O	12	-40 °C (-40 °F)	Tin Lead	Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops	e0	55.6 MHz			29.21 mm	No	37
XC7336-12WC44I	Xilinx	UV PLD	Industrial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	19 ns	Yes	5.5 V	36	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 32 I/O	2	-40 °C (-40 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops		80 MHz			16.51 mm	No	32
XC73108-20PG144C	Xilinx	UV PLD	Commercial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.25 V	108	CMOS				5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.75 V		2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz			39.624 mm	No	78
XC7272A-16WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	25 ns	Yes	5.5 V	72	CMOS				5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 38 I/O	8	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		55 MHz			24.13 mm	No	38
XC7354-7WC44C	Xilinx	UV PLD	Commercial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	16.5 ns	Yes	5.25 V	54	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	8 Dedicated Inputs, 25 I/O	8	0 °C (32 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 108 Flip Flops		95.2 MHz			16.51 mm	No	25
XC7236A-20WC44M	Xilinx	UV PLD	Military	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V	36	CMOS				5	3/5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	125 °C (257 °F)	2 Dedicated Inputs, 30 I/O	2	-55 °C (-67 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	PAL Blocks interconnected by PIA; 36 Macrocells; Configurable I/O operation with 3.3 V or 5 V		40 MHz			16.51 mm	No	30
XC7272-25PG84I	Xilinx	UV PLD	Industrial	Pin/Peg	84	PGA	Square	Ceramic	40 ns	No		72	CMOS				5	5 V	Grid Array	PGA84M,11X11	Programmable Logic Devices	No				2.54 mm	85 °C (185 °F)			-40 °C (-40 °F)		Perpendicular	S-XPGA-P84				No							No
XC73108-15PG144C	Xilinx	UV PLD	Commercial	Pin/Peg	144	WPGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.25 V	108	CMOS				5	3.3/5,5 V	Grid Array, Window	PGA144,15X15	Programmable Logic Devices	No	Macrocell	4.75 V		2.54 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Perpendicular	S-CPGA-P144	1	3.683 mm	39.624 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		45.5 MHz			39.624 mm	No	78
XC7354-15WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V	54	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 42 I/O	8	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	54 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 108 Flip Flops		55.6 MHz			24.13 mm	No	42
XC73144-15PG184C	Xilinx	UV PLD	Commercial	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.25 V		CMOS				5		Grid Array				Macrocell	4.75 V			70 °C (158 °F)	0 Dedicated Inputs, 120 I/O	0	0 °C (32 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		45.5 MHz					120
XC7336Q-15WC44I	Xilinx	UV PLD	Industrial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	23 ns	Yes	5.5 V	36	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 32 I/O	2	-40 °C (-40 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops		66.7 MHz			16.51 mm	No	32
XC7236A-25WC44I	Xilinx	UV PLD	Industrial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	40 ns	Yes	5.5 V	36	CMOS				5	3/5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	2 Dedicated Inputs, 30 I/O	2	-40 °C (-40 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	PAL Blocks interconnected by PIA; 36 Macrocells; Configurable I/O operation with 3.3 V or 5 V		33 MHz			16.51 mm	No	30
XC7272A-25WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	40 ns	Yes	5.5 V	72	CMOS				5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	8 Dedicated Inputs, 38 I/O	8	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		40 MHz			24.13 mm	No	38
XC7336Q-15WC44C	Xilinx	UV PLD	Commercial	J Bend	44	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	23 ns	Yes	5.25 V	36	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC44,.7SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	2 Dedicated Inputs, 32 I/O	2	0 °C (32 °F)		Quad	S-CQCC-J44	1	4.826 mm	16.51 mm	No	36 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 2 External Clocks; 36 Flip Flops		66.7 MHz			16.51 mm	No	32
XC73144-15PG184M	Xilinx	UV PLD	Military	Pin/Peg	184	PGA	Square	Ceramic, Metal-Sealed Cofired	36 ns	No	5.5 V		CMOS				5		Grid Array				Macrocell	4.5 V			125 °C (257 °F)	0 Dedicated Inputs, 120 I/O	0	-55 °C (-67 °F)		Perpendicular	S-CPGA-P184				No	144 Macrocells With Programmable I/O Architecture		45.5 MHz					120
XC7272-30WC84I	Xilinx	UV PLD	Industrial	J Bend	84	QCCJ	Square	Ceramic	48 ns	Yes		72	CMOS				5	5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No				1.27 mm	85 °C (185 °F)			-40 °C (-40 °F)		Quad	S-XQCC-J84				No							No
XC73108-20WB225C	Xilinx	UV PLD	Commercial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	Yes	5.25 V	108	CMOS				5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.75 V		1.5 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Bottom	S-CBGA-B225	1			No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		35.7 MHz				No	78
XC7272A-20WC84I	Xilinx	UV PLD	Industrial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	32 ns	Yes	5.5 V	72	CMOS				5	5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	12 Dedicated Inputs, 42 I/O	12	-40 °C (-40 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	PAL Blocks interconnected by PIA; 72 Macrocells		50 MHz			29.21 mm	No	42
XC7372-15WC68I	Xilinx	UV PLD	Industrial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	33 ns	Yes	5.5 V	72	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.5 V		1.27 mm	85 °C (185 °F)	10 Dedicated Inputs, 25 I/O	10	-40 °C (-40 °F)		Quad	S-CQCC-J68	1	4.826 mm	24.13 mm	No	72 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 126 Flip Flops		52.6 MHz			24.13 mm	No	25
XC73108-12WB225C	Xilinx	UV PLD	Commercial	Ball	225	WBGA	Square	Ceramic, Metal-Sealed Cofired	30 ns	Yes	5.25 V	108	CMOS				5	3.3/5,5 V	Grid Array, Window	BGA225,15X15	Programmable Logic Devices	No	Macrocell	4.75 V		1.5 mm	70 °C (158 °F)	12 Dedicated Inputs, 78 I/O	12	0 °C (32 °F)		Bottom	S-CBGA-B225	1			No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		55.6 MHz				No	78
XC7272-30WC84C	Xilinx	UV PLD	Commercial	J Bend	84	QCCJ	Square	Ceramic	48 ns	Yes		72	CMOS				5	5 V	Chip Carrier	LDCC84,1.2SQ	Programmable Logic Devices	No				1.27 mm	70 °C (158 °F)			0 °C (32 °F)		Quad	S-XQCC-J84				No							No
XC73108-12WC84C	Xilinx	UV PLD	Commercial	J Bend	84	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	30 ns	Yes	5.25 V	108	CMOS				5	3.3/5,5 V	Chip Carrier, Window	LDCC84,1.2SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	12 Dedicated Inputs, 37 I/O	12	0 °C (32 °F)		Quad	S-CQCC-J84	1	4.826 mm	29.21 mm	No	108 Macrocells; Configurable I/O operation with 3.3 V or 5 V; 3 External Clocks; 198 Flip Flops		55.6 MHz			29.21 mm	No	37
PLX464WJC-45	Broadcom	UV PLD	Commercial	J Bend	28	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	45 ns	Yes	5.25 V	8	CMOS		26	PAL-TYPE	5	5 V	Chip Carrier, Window	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.75 V	88	1.27 mm	70 °C (158 °F)	9 Dedicated Inputs, 8 I/O	9	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J28		5.59 mm	11.6332 mm	No	PAL with Macrocells; 8 Macrocells; 2 External Clocks; Shared Input/Clock	e0	16.7 MHz	8		11.6332 mm		8
PLX448M-65	Broadcom	UV PLD	Military	Through-Hole	24	WDIP	Rectangular	Ceramic, Glass-Sealed	65 ns	No	5.5 V	8	CMOS		26	PAL-TYPE	5	5 V	In-Line, Window	DIP24,.3	Programmable Logic Devices		Macrocell	4.5 V	88	2.54 mm	125 °C (257 °F)	9 Dedicated Inputs, 8 I/O	9	-55 °C (-67 °F)	Tin Lead	Dual	R-GDIP-T24		5.3 mm	7.62 mm	No	PAL with Macrocells; 8 Macrocells; 2 External Clocks; Shared Input/Clock	e0	11.1 MHz	8		32.2 mm		8
EP610DC24-25	Altera	UV PLD	Commercial	Through-Hole	24	WDIP	Rectangular	Ceramic, Glass-Sealed	27 ns	No	5.25 V		CMOS		20	PAL-TYPE	5	5 V	In-Line, Window	DIP24,.3	Programmable Logic Devices		Macrocell	4.75 V	160	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)	Tin Lead	Dual	R-GDIP-T24		5.08 mm	7.62 mm	No	16 Macrocells; 2 External Clocks	e0	47.6 MHz	16	220 °C (428 °F)	32 mm		16
EPM5130AGC-15	Altera	UV PLD	Commercial	Pin/Peg	100	WPGA	Square	Ceramic, Metal-Sealed Cofired	25 ns	No	5.25 V		CMOS				5		Grid Array, Window				Macrocell	4.75 V		2.54 mm	70 °C (158 °F)	19 Dedicated Inputs, 64 I/O	19	0 °C (32 °F)		Perpendicular	S-CPGA-P100		3.81 mm	33.528 mm	No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock		83.3 MHz			33.528 mm		64
EP320DC-2	Altera	UV PLD	Commercial	Through-Hole	20	WDIP	Rectangular	Ceramic, Glass-Sealed	35 ns	No	5.25 V		CMOS		18	PAL-TYPE	5	5 V	In-Line, Window	DIP20,.3	Programmable Logic Devices		Macrocell	4.75 V	72	2.54 mm	70 °C (158 °F)	9 Dedicated Inputs, 8 I/O	9	0 °C (32 °F)	Tin Lead	Dual	R-GDIP-T20		4.826 mm	7.62 mm	No	8 Macrocells; Shared Input/Clock	e0	40 MHz	8	220 °C (428 °F)	24.003 mm		8
EP610DC24-35	Altera	UV PLD	Commercial	Through-Hole	24	WDIP	Rectangular	Ceramic, Glass-Sealed	37 ns	No	5.25 V		CMOS		20	PAL-TYPE	5	5 V	In-Line, Window	DIP24,.3	Programmable Logic Devices		Macrocell	4.75 V	160	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)	Tin Lead	Dual	R-GDIP-T24		5.08 mm	7.62 mm	No	16 Macrocells; 2 External Clocks	e0	37 MHz	16	220 °C (428 °F)	32 mm		16
EPM5128GI-2	Altera	UV PLD	Industrial	Pin/Peg	68	PGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V	128	CMOS				5	5 V	Grid Array	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V		2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1			No	Labs interconnected by PIA; 8 Labs; 128 Macrocells; 1 External Clock; Shared Input/Clock	e0	40 MHz		220 °C (428 °F)		No	52
EP610DI-15	Altera	UV PLD	Industrial	Through-Hole	24	DIP	Rectangular	Ceramic, Glass-Sealed	15 ns	No	5.5 V						5		In-Line				Macrocell	4.5 V			85 °C (185 °F)	4 Dedicated Inputs, 16 I/O	4	-40 °C (-40 °F)		Dual	R-GDIP-T24				No			83.3 MHz					16
EP610DI-30	Altera	UV PLD	Industrial	Through-Hole	24	DIP	Rectangular	Ceramic, Glass-Sealed	32 ns	No	5.5 V		CMOS		20	PAL-TYPE	5	5 V	In-Line	DIP24,.3	Programmable Logic Devices		Macrocell	4.5 V	160	2.54 mm	85 °C (185 °F)	4 Dedicated Inputs, 16 I/O	4	-40 °C (-40 °F)	Tin Lead	Dual	R-GDIP-T24				No	Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks	e0	33.3 MHz	16	220 °C (428 °F)			16
EPM5192GC84-2	Altera	UV PLD	Commercial	Pin/Peg	84	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.25 V		CMOS				5		Grid Array, Window				Macrocell	4.75 V		2.54 mm	70 °C (158 °F)	7 Dedicated Inputs, 64 I/O	7	0 °C (32 °F)		Perpendicular	S-CPGA-P84		4.96 mm	28.448 mm	No	192 Macrocells; Shared Input/Clock; Shared Product Terms		40 MHz			28.448 mm		64
EPM5128GI68-2	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	45 ns	No	5.5 V		CMOS				5		Grid Array, Window				Macrocell	4.5 V		2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)		Perpendicular	S-CPGA-P68		4.96 mm	27.94 mm	No	128 Macrocells; 8 Labs		50 MHz			27.94 mm		52
EP220DC-10A	Altera	UV PLD	Commercial	Through-Hole	20	DIP	Rectangular	Ceramic, Glass-Sealed	10 ns	No	5.25 V		CMOS		18	PAL-TYPE	5	5 V	In-Line	DIP20,.3	Programmable Logic Devices		Macrocell	4.75 V	72	2.54 mm	70 °C (158 °F)	9 Dedicated Inputs, 8 I/O	9	0 °C (32 °F)	Tin Lead	Dual	R-GDIP-T20				No	8 Macrocells	e0	111 MHz	8	220 °C (428 °F)			8
EP600JM883B	Altera	UV PLD	Military	J Bend	28	QCCJ	Square	Ceramic, Metal-Sealed Cofired	55 ns	Yes	5.5 V		CMOS	MIL-STD-883 Class B	20	PAL-TYPE	5	5 V	Chip Carrier	LDCC28,.5SQ	Programmable Logic Devices		Macrocell	4.5 V	160	1.27 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)	Tin Lead	Quad	S-CQCC-J28		4.57 mm	11.43 mm	No	16 Macrocells	e0	22.2 MHz	16	220 °C (428 °F)	11.43 mm		16
EPM5128GI68	Altera	UV PLD	Industrial	Pin/Peg	68	WPGA	Square	Ceramic, Metal-Sealed Cofired	55 ns	No	5.5 V	128	CMOS				5	5 V	Grid Array, Window	PGA68,11X11	Programmable Logic Devices	No	Macrocell	4.5 V		2.54 mm	85 °C (185 °F)	7 Dedicated Inputs, 52 I/O	7	-40 °C (-40 °F)	Tin Lead	Perpendicular	S-CPGA-P68	1	4.96 mm	27.94 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e0	33.3 MHz		220 °C (428 °F)	27.94 mm	No	52
EP610DM-35	Altera	UV PLD	Military	Through-Hole	24	WDIP	Rectangular	Ceramic, Glass-Sealed	37 ns	No	5.5 V		CMOS		20	PAL-TYPE	5	5 V	In-Line, Window	DIP24,.3	Programmable Logic Devices		Macrocell	4.5 V	160	2.54 mm	125 °C (257 °F)	4 Dedicated Inputs, 16 I/O	4	-55 °C (-67 °F)	Tin Lead	Dual	R-GDIP-T24		5.334 mm	7.62 mm	No	Macrocells Interconnected By Global Bus; 16 Macrocells; 2 External Clocks	e0	28.6 MHz	16	220 °C (428 °F)	31.75 mm		16
EP610IDC-25	Altera	UV PLD	Commercial	Through-Hole	24	WDIP	Rectangular	Ceramic, Glass-Sealed	25 ns	No	5.25 V		CMOS		20	PAL-TYPE	5	5 V	In-Line, Window	DIP24,.3	Programmable Logic Devices		Macrocell	4.75 V	160	2.54 mm	70 °C (158 °F)	4 Dedicated Inputs, 16 I/O	4	0 °C (32 °F)	Tin Lead	Dual	R-GDIP-T24		5.08 mm	7.62 mm	No		e0	40 MHz	16	220 °C (428 °F)	32 mm		16
EP910IDI-15	Altera	UV PLD	Industrial	Through-Hole	40	WDIP	Rectangular	Ceramic, Glass-Sealed	18 ns	No	5.5 V		CMOS		36	PAL-TYPE	5	5 V	In-Line, Window	DIP40,.6	Programmable Logic Devices		Macrocell	4.5 V	450	2.54 mm	85 °C (185 °F)	12 Dedicated Inputs, 24 I/O	12	-40 °C (-40 °F)	Tin Lead	Dual	R-GDIP-T40		5.75 mm	15.24 mm	No	Macrocells Interconnected By Global Bus; 24 Macrocells; 2 External Clocks	e0	66.6 MHz	24	220 °C (428 °F)	52.07 mm		24
EPS448DM28-20	Altera	UV PLD	Military	Through-Hole	28	WDIP	Rectangular	Ceramic, Glass-Sealed		No	5.5 V		CMOS				5		In-Line, Window				Registered	4.5 V		2.54 mm	125 °C (257 °F)	8 Dedicated Inputs, 0 I/O	8	-55 °C (-67 °F)		Dual	R-GDIP-T28		5.08 mm	7.62 mm	No	PLS		20 MHz			36.83 mm		0
EPM5128JC68-1	Altera	UV PLD	Commercial	J Bend	68	WQCCJ	Square	Ceramic, Metal-Sealed Cofired	40 ns	Yes	5.25 V	128	CMOS				5	5 V	Chip Carrier, Window	LDCC68,1.0SQ	Programmable Logic Devices	No	Macrocell	4.75 V		1.27 mm	70 °C (158 °F)	7 Dedicated Inputs, 52 I/O	7	0 °C (32 °F)	Tin Lead	Quad	S-CQCC-J68		5.08 mm	24.13 mm	No	128 Macrocells; Shared Input/Clock; Shared Product Terms	e0	50 MHz		220 °C (428 °F)	24.13 mm	No	52

Programmable Logic Devices (PLD)

Programmable Logic Devices (PLDs) are digital circuits that are designed to be programmed by the user to perform specific logic functions. They consist of an array of configurable logic blocks (CLBs) that can be programmed to perform any digital function, as well as programmable interconnects that allow these blocks to be connected in any way the designer wishes. This makes PLDs highly versatile and customizable, and they are often used in applications where a high degree of flexibility and performance is required.

PLDs are programmed using specialized software tools that allow the designer to specify the logic functions and interconnects that are required for a particular application. This process is known as synthesis and involves translating the high-level design into a format that can be implemented on the PLD hardware. The resulting configuration data is then loaded onto the PLD, allowing it to perform the desired logic functions.

PLDs are used in a wide range of applications, including digital signal processing, computer networking, and high-performance computing. They offer a number of advantages over traditional fixed-function digital circuits, including the ability to be reprogrammed in the field, lower development costs, and faster time-to-market. However, they also have some disadvantages, including higher power consumption and lower performance compared to custom-designed digital circuits.